In my opinion it is very good option to have 64 PINs version of Prop 1
Prop II is diferent CPU with only same structure.
First. It is 3.3 V version chip not 1.x V
Second It is fuly program compatible with Prop 1.
My only question is. Have You reconstructed PLLs?
▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔ Nothing is impossible, there are only different degrees of difficulty. For every stupid question there is at least one intelligent answer. Don't guess - ask instead. If you don't ask you won't know. If your gonna construct something, make it·as simple as·possible yet as versatile as posible.
One thing that a 64 pin Prop I would open up would be large directly addressable SRAM and applications that might need that. It would be easy to add a 512K byte SRAM to I/O port B with high speed access.
I suppose cost is another consideration... If the chip would cost twice as much, I'd have to think about if it'd be better to use two regular Prop 1's with a common clock...
64 pins sounds great. The exact format doesn't really matter as adaptors are easy to make (eg after a quick search I found a 48 pin SSOP to DIP board on ebay for $2.19). PLCC is another choice. Whatever format works out cheapest. 64 pins opens up the possibility of big SRAM and vga/mouse/keyboard/audio/SDCard all on one chip instead of having to use two or more Props. I'm sure someone would come up with a protoboard to do that. Anything smaller than standard surface mount would probably be better coming pre soldered to a protoboard. As for recouping development costs, there are still untapped markets for the Propeller. Here in Australia we have just one supplier and zero articles in the mainstream electronics press.
Propeller I 64 I/Os?
Yes, if costs the same as Propeller I
Chip, be careful, if the price enlarges could not be competitive against the new one Propeller II (that in the end will have 64 I/O and more power)
Part of the problem was/is question of time: If it had been ready today, then there is not problem, but we will have now two chips (64 I/Os) at the same time ¿Which will prefer the people?
Nobody knows, but personally I prefer Propeller I 32 I/O, for the smaller tasks and Propeller II for the largest things.
If the investment for Parallax is not signifier or you think that will be all a success, ahead!
In theory, I am all for a 64 i/o Prop I. In practice, I will only buy it already on a board. I would need a board like the Proto Board and would also like an adaptor to use the new chip with the Propeller Professional Development board (similar to the BS2P24/40 Adapter Board). I would not be upset with a $10-15 price premimum.
How long before we see the Prop I-64?·· (I presume it would take about 3 months?)
How long before we see the Prop II-64?· (I presume you are still 12 months away?)
I don't think the Prop I-64 will take market away from the Prop II as those wanting the power will go for it as soon as it is available. The Prop I-64 will solve many current issues such as more pins for all sorts of things, but immediately it will allow 128KB-2MB SRAM or 8MB SDRAM to be added.
The old Prop I(-32) will remain for those wishing to experiment with the DIP package by soldering themselves. Or by using a daughter board with the Prop I-64 and holes for the user to mount to their own board. You have said that adding the pins (like on the stamp) are expensive, so just allow holes for the user to solder pin stakes to.
The new ProtoBoard USB·(presume Parallax will do one) could have the Prop I-64 and optional (fitted or unfitted options) of the·8MB SDRAM (M48LC32M8A2 in 54TSOP). As long as there is prototype area for the 36 DIP for 128KB-2MB SRAM, the user can wire this themselves.
If you do this Prop I-64 then could the Prop II have:
(I don't know the impact on lead time and where you are up to, but presume you are into the hub from your postings)
* More cogs (16) at the expense of some hub ram and rom? (I still see this as an issue, especially with external memory and microSD cards)
* More than 64 pins so that the SDRAM or SRAM could be used without impacting the 64 I/O pins. I guess what I am asking for is a hub memory controller accessed by a·cog to hub RD/WR style command.
(We are stuck with SMT so the package is not so much of a problem as long as someone places it on a daughterboard)
Alternately, could 8 older Prop I cogs (smaller footprint than the Prop II cogs)·be added to the Prop II with a slower hub access?
▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔ Links to other interesting threads:
soldering surface mount is not hard by hand. just do outside 2 pins then lightly apply solder and heat to each quickly. I am sure if chip makes the ic then someone will sell it already attached to the pcb. If no one else will I will.
I love the idea, it would definitely help me - however it largely depends on:
1) price (should not be more than 1.5x current prop)
2) package (SMD soldering of 0.05" is fine, 1mm is doable, smaller is painful - at least for me) PLCC84 would be nice [noparse]:)[/noparse]
Frankly, I would also love a 28 pin dip version of the prop, say
P0-P15, P24-P31, -RST, OSCIN, Vdd, Vss
▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔ www.mikronauts.com - a new blog about microcontrollers
@ All: IIRC the packaging prices and availibility from viewing it on Chip's monitor over a year ago, I don't think PLCC is an option. It was either not availible or was really expensive (I don't remeber which, but I do rememeber specifically looking for it and being disappointed). But don't go on my word wrt this, my memory has failed me in the past. Regardless of what package they use, they will make availible a hobbyist friendly way to use it, it is Parallax after all.
@ Chip: I agree with many people's opinion of making RAM expansion very easy, but given the current economy and the cost of getting the Prop B to market, I think this is a decision that requires some market analysis. How much you'd have to sell it for, how much the Prop 2 would sell for and see if there would be enough of a valley between the Prop 1 and Prop 2 to warrent the Prop B. The worst would be seeing· decent sales at it's unveiling only to see it drop to nothing once the Prop 2 is out. Hobbyists will always say they want more options but it's volume sales over time that make or break a product.
Back @ All: rather than just answering if you want 64 I/O pins seriously consider if you would buy (and even more important build products around) the Prop B once the Prop 2 is out. Cole and Cluso99 have the right idea in thier answers, they're not just considering the # of I/O pins but applications where it's preferable that the chip has lower power.
Something else to keep in mind ... The Prop 2 will require another voltage regulator. It's not a big deal, but it is one more piece. Also, existing designs can be easily redone for the larger pinout. For that matter, an adapter can be made that plugs into a DIP Prop I socket with an extra header with the other 32 I/O pins much like the BS2p40 adapter if there's a need or market for it. Whether the $80K can be justified is a whole 'nother question.
Paul Baker said...
@ All: IIRC the packaging prices and availibility from viewing it on Chip's monitor over a year ago, I don't think PLCC is an option. It was either not availible or was really expensive (I don't remeber which, but I do rememeber specifically looking for it and being disappointed). But don't go on my word wrt this, my memory has failed me in the past. Regardless of what package they use, they will make availible a hobbyist friendly way to use it, it is Parallax after all.
All I care about is that it be hand-solderable by mere mortals. PLCC, SOJ, anything with leads with 1mm or greater spacing please
Paul Baker said...
@ Chip: I agree with many people's opinion of making RAM expansion very easy, but given the current economy and the cost of getting the Prop B to market, I think this is a decision that requires some market analysis. How much you'd have to sell it for, how much the Prop 2 would sell for and see if there would be enough of a valley between the Prop 1 and Prop 2 to warrent the Prop B. The worst would be seeing decent sales at it's unveiling only to see it drop to nothing once the Prop 2 is out. Hobbyists will always say they want more options but it's volume sales over time that make or break a product.
(taking out crystal ball, talking qty.1 US pricing)
Prop 1 is $13
Prop 1-64 at $15 would probably sell like hotcakes, would probably sell ok at $18, but would not sell above that
Prop 2 at $20 would sell well, would sell ok at $25, would move very slowly at $30, and higher would be disaster
(putting away crystal ball)
Paul Baker said...
Back @ All: rather than just answering if you want 64 I/O pins seriously consider if you would buy (and even more important build products around) the Prop B once the Prop 2 is out. Cole and Cluso99 have the right idea in thier answers, they're not just considering the # of I/O pins but applications where it's preferable that the chip has lower power.
Depends on the project. 64 I/O and low power would be a winner for many designs where Prop I might now need an AVR or two, or SPI peripherals.
Prop 2 will be wonderful, slice bread, etc, but Prop 1-64 will be "good enough" for a fair set of problems.
The real question is... how many units does parallax need to ammortize the 80k over?
▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔ www.mikronauts.com - a new blog about microcontrollers
Another thing that might work out well is to have pin compatible packages between Prop B and Prop II. Like mike said, prop II would require another pin for the 1.8V regulator, but that could be mapped to another 3.3V power pin on a Prop B, or NC at all.
I for one, would take 4 Prop B Proto boards at $50 each if they are anything like the protoboards we have now. Those things are very handy.
Here's where I see great advantages to Prop B:
1. Connection to RAM.
2. More pins to connect high speed buses in multiprop designs.
3. Maybe eliminate the need for some multiprop design(how many times have people run out of cogs only to find that they could double up on tasks/cog?)
4. Downsizing/simplifying current designs because ram #1 ...Like the Extreme Memory expansion, OpenStomp, etc.
5. No learning curve for those that just need more pins or ram, not more processing power(I for one, have not done assembly on a pipelined processor and tried to calculate clock ticks for loops)
I for one, after thinking about it, agree with cluzo's "I guess what I am asking for is a hub memory controller accessed by a cog to hub RD/WR style command." in Prop II.
It would open up the possibilities of the chip to be used in many industrial designs where ARM and MIPS are common right now because they have a descent processing power and access to lots of SDRAM ie: Cable Routers and other network devices.
It sure would be simpler for those with large memory needs to keep things coherent than 3 levels of memory. I like simple. I like the propeller.
I don't know if it is way late to be bringing up such things in the design cycle of the Prop II, but you probably have thought that through already.
@Bill: Yeah, you could put 8 of them in parallel, but that sure would be a lot wasted cycles as each one would have to have the addresses loaded serially into each chip 8 times in parallel.
Please stick to your original plan. The memory controller is a right idea at the right time.
Do you need help finalizing the design? Your design seems to be getting away with being all things to all people.
Please don't design by committee - KISS principle is best.
hinv said...
@Bill: Yeah, you could put 8 of them in parallel, but that sure would be a lot wasted cycles as each one would have to have the addresses loaded serially into each chip 8 times in parallel.
Totally agree! But it is barely possible, and the only way I could see doing it with SPI ram for any sort of screen buffer
Having an additional 32 bits of fast I/O certainly does open possibilities...
▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔ www.mikronauts.com - a new blog about microcontrollers
so would a asembly command "increment and roll to 0 if = x" I use that a lot more often then max or min. But that is aside note. I would definetly buy a prop 2 with 64bit io. I want to be able to run a 1600x1200 LCD monitor in full colour.
Here's an idea, don't know if it's technically feasible or not: connect the hub ram address and data lines out to the B port pins; make it so that port B can EITHER be general purpose i/o OR a memory controller, but not both. Use all 32 port B pins for direct connection to address, data, and read/write pins (making Propeller 2 act somewhat like microprocessor rather than microcontroller). You'd still have port A which is what most software will default to supporting anyhow (especially software originally written for Prop 1). You'd need more hub address lines to access all 32 MB, but your layout probably would be screwed up by trying to have all the extra address lines to all cogs, so instead, make it so the user can map a 64K window of hub ram to DRAM, and set the higher address bytes with a register and/or counter.
Edit: In my Prop6502 laptop, you could map sections of 6502 RAM to go to the Propeller's hub RAM instead of the external SRAM chip; this would be like that, but in reverse.
Edit 2: Or would it be cleaner to have an instruction, like RDBYTE but not the same code, for reading external RAM?
Post Edited (Dennis Ferron) : 1/30/2009 5:48:02 AM GMT
We cannot ask for anything on the Prop I-64 other than the pins, else it will delay the production. I fear Prop II is still some time away, so this might be the intermediate answer, and provides lots of options with the low power we already have. I cannot address the cost to Parallax.
For the Prop I-64, there are cheapish 4Mb-64Mbit SPI Flash available with 2 pin fast reads (W25X32 from Digikey about $2.80). SRAM in 128KB, 512KB (32DIP AS6C1008, AS6C4008 about $4, $9) and 2MByte (the 2MB is v.low power and battery backed internally 32DIP· M48Z2M1V about $150 from Digikey - ouch) as well as Chip's SDRAM 32MByte. These can all be easily interfaced with the extra pins.
I know no-one wants to here this, but IMHO, it would relieve some of the pressure on the Prop II so that we could get some extra features like the SRAM/SDRAM interface as a pseudo hub access instruction. Chip, if you do, please add more pins for this interface (i.e. plus 64 I/O), and pretty please... more cogs (new or old style) because this chip is going to fly. With the Prop I-64, the Prop II can withstand a higher price so·you could have the extra die space required.
@Quantum: I am well on the way with the layout - hope to send it away for mfg before I get tied up next week. :-)
@Dennis: The SDRAM only uses 29/30 pins as it is multiplexed RAS/CAS·(for bytewide). For SRAM 4MByte can be addressed with 32 pins (or 8MByte if CE tied low). Hub access uses 32 bit addresses (bytewise), just the extra bits are ignored (unsure whether it wraps or not).
▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔ Links to other interesting threads:
Dennis Ferron said...
Here's an idea, don't know if it's technically feasible or not: connect the hub ram address and data lines out to the B port pins; make it so that port B can EITHER be general purpose i/o OR a memory controller, but not both. Use all 32 port B pins for direct connection to address, data, and read/write pins (making Propeller 2 act somewhat like microprocessor rather than microcontroller). You'd still have port A which is what most software will default to supporting anyhow (especially software originally written for Prop 1). You'd need more hub address lines to access all 32 MB, but your layout probably would be screwed up by trying to have all the extra address lines to all cogs, so instead, make it so the user can map a 64K window of hub ram to DRAM, and set the higher address bytes with a register and/or counter.
Edit: In my Prop6502 laptop, you could map sections of 6502 RAM to go to the Propeller's hub RAM instead of the external SRAM chip; this would be like that, but in reverse.
Edit 2: Or would it be cleaner to have an instruction, like RDBYTE but not the same code, for reading external RAM?
Yeah, I was thinking that a cog program would have to initialize the SDRAM, since it's pretty complicated and would be a waste of hardware. Then, an extra·state machine, similar to the hub, could take over and manipulate those I/O pins to perform the CAS/RAS/ADDR/DATA/etc business required for reads and writes. The cogs could then access·the SDRAM·using regular RDxxxx/WRxxxx instructions, differentiated from normal hub accesses by address range. There would need to be some separate internal address and data buses to support this, so that the regular hub buses wouldn't be stalled by the different SDRAM sequencing.
This SDRAM is attractive because of its density/price, but random-access performance is pretty lousy due to all the RAS/CAS and delay cycles required before data comes out. Once is starts coming out, though, you can get a big stream pretty quickly. Now I·have a better understanding of·just why Pentiums must have large internal caches to get high performance. A cache is quite a silicon commitment and I don't think it's the kind of thing that belongs in a Propeller chip.
Thanks Chip!. That would be great! Caches... they may not be that necessary... there are HUB and COG memory around anyways. A SDRAM controller that can also use SRAM will be very nice. As low power as SDRAM can be, SRAMs are still lower power.
And do not forget the 64 IOs Propeller I!
Great news Chip. Yes, the Prop is not a Pentium and cache is not required.
We just need access to more memory and if you can handle both SRAM and SDRAM (select one or the other when initialising the controller) it can be initialised by a cog and left to run. There would be an advantage to be able have the hub load a block of SDRAM into the hub (or cog?) using the controller to do an automatic burst mode.
▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔ Links to other interesting threads:
Yeah, I was thinking that a cog program would have to initialize the SDRAM, since it's pretty complicated and would be a waste of hardware. Then, an extra state machine, similar to the hub, could take over and manipulate those I/O pins to perform the CAS/RAS/ADDR/DATA/etc business required for reads and writes. The cogs could then access the SDRAM using regular RDxxxx/WRxxxx instructions, differentiated from normal hub accesses by address range. There would need to be some separate internal address and data buses to support this, so that the regular hub buses wouldn't be stalled by the different SDRAM sequencing.
This SDRAM is attractive because of its density/price, but random-access performance is pretty lousy due to all the RAS/CAS and delay cycles required before data comes out. Once is starts coming out, though, you can get a big stream pretty quickly. Now I have a better understanding of just why Pentiums must have large internal caches to get high performance. A cache is quite a silicon commitment and I don't think it's the kind of thing that belongs in a Propeller chip.
Using RDBYTE/RDWORD you could even allow for a 16 bit data bus
It would also be very nice to have an SRAM mode, 10ns SRAMS are readily available at fairly decent prices, with a bit more circuitry it would allow for say a 16 cycle hub like shared external memory as two clocks should be enough to read/write the external 10ns (or 7ns) sram, and by having a 2 clock window for xram eight cogs could be serviced in 16 clocks... leading to a design where hub accesses are in 8 clocks, and xram access is in 16 clocks.
Combine that with a 16 bit external data bus, and there would be potentially 80x2 = 160MB/sec memory bandwidth (combined, for all cogs, ie 20MB/sec per cog, same bandwidth as current hub memory bandwidth on Prop 1!)
I think something like:
B0-B15 = data bus
B16-B27 = 12 bit address bus
B28 = -ALE / -RAS (as ALE, latch B16-B27 into external latches, for more address lines, also latch B0-B15)
B29 = RD
B30 = WR_LO
B31 = WR_HI
(I know, we'd have to steal a pin from Port A for CAS, unless of course you had dedicated -RAS/-CAS/-RD/-WRL/-WRH pins outside of the normal port B, in which case B28-B31 could be used for "bank" or additional address bits)
The only down side is an additional clock required to latch the upper part of the address when it changes.
Food for thought...
actually, it may be better to have the memory window for XRAM to be 24 cycles - that would allow for strobing a new high address for each cogs cycle, AND it would allow for double reads/writes needed to support RDLONG and WRLONG
160MHz/24 cycles = 6.66M cog-accesses (per cog) per second, using LONG's that would be 26.6MB/sec bandwidth, greater than current hub bandwidth
20 cycle windows may be possible, and that would be even better:
160MHz/20 cycles = 8M cog accesses (per cog) per second, using longs it would be 32MB/sec bandwidth per cog
1024x768x8 bit VGA needs about 48-60MB/sec to feed... two cogs would have enough bandwidth!
▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔ www.mikronauts.com - a new blog about microcontrollers
Post Edited (Bill Henning) : 1/30/2009 3:30:49 PM GMT
Unless there are a lot of sales on the table, the cost for 64 pin Prop I doesn't seem to make sense.
Re: Cache
Seems to me, the design of the Propeller is kind of like a CPU with cache and such already. If there is external RAM, and if there are limits on it that exceed HUB limits, then a COG or two could be managing that, leaving the HUB memory to be essentially a cache anyway, particularly where LMM kinds of programs are concerned.
It really depends on profit margins, and I don't expect parallax to disclose those.
I would really like to see it personally, but I am not going to pay the $80k, but as I said, I would pay $50 for a Prob B USB ProtoBoard, in fact take 4 of them.
Re: Cache,
Yes it is currently like that. With external ram + hub ram + cog ram, there is more to keep coherent which adds complexity, burns cycles, etc. I really like the cog ram plus ram controller for hub idea for SRAM, but as Chip was saying for SDRAM, there would need to be some kind of cache, which would kind of mess up determinism. Yes, it is deterministic, but it depends on the state of the cache how far you are reaching to a different address....
When it comes to memory architectures, my favorite is UMA like in the SGI O2 which is somewhat like the current prop. http://www.futuretech.blinkenlights.nl/o2arch.html http://en.wikipedia.org/wiki/SGI_O2
Big memory has some definite advantages when reaching into other markets. I for one would like to see the propeller reach into markets that are now dominated by MIPS and ARM, and most of these have big ram.
Seems like·a marketing plan that goes way beyond the Parallax Niche, would be necessary to justify a 64 pin device (seems like·a significant gamble, trying to break out of your mold). I've always thought that just 4 to 8 additional pins to allow flexible Prop to Prop communications, would be easier.
Comments
In my opinion it is very good option to have 64 PINs version of Prop 1
Prop II is diferent CPU with only same structure.
First. It is 3.3 V version chip not 1.x V
Second It is fuly program compatible with Prop 1.
My only question is. Have You reconstructed PLLs?
▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
Nothing is impossible, there are only different degrees of difficulty.
For every stupid question there is at least one intelligent answer.
Don't guess - ask instead.
If you don't ask you won't know.
If your gonna construct something, make it·as simple as·possible yet as versatile as posible.
Sapieha
Yes, if costs the same as Propeller I
Chip, be careful, if the price enlarges could not be competitive against the new one Propeller II (that in the end will have 64 I/O
Part of the problem was/is question of time: If it had been ready today, then there is not problem, but we will have now two chips (64 I/Os) at the same time ¿Which will prefer the people?
Nobody knows, but personally I prefer Propeller I 32 I/O, for the smaller tasks and Propeller II for the largest things.
If the investment for Parallax is not signifier or you think that will be all a success, ahead!
"My two cents"
Rgds,
John Twomey
▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
'Necessity is the mother of invention'
Those who can, do.Those who can’t, teach.
John Abshier
How long before we see the Prop II-64?· (I presume you are still 12 months away?)
I don't think the Prop I-64 will take market away from the Prop II as those wanting the power will go for it as soon as it is available. The Prop I-64 will solve many current issues such as more pins for all sorts of things, but immediately it will allow 128KB-2MB SRAM or 8MB SDRAM to be added.
The old Prop I(-32) will remain for those wishing to experiment with the DIP package by soldering themselves. Or by using a daughter board with the Prop I-64 and holes for the user to mount to their own board. You have said that adding the pins (like on the stamp) are expensive, so just allow holes for the user to solder pin stakes to.
The new ProtoBoard USB·(presume Parallax will do one) could have the Prop I-64 and optional (fitted or unfitted options) of the·8MB SDRAM (M48LC32M8A2 in 54TSOP). As long as there is prototype area for the 36 DIP for 128KB-2MB SRAM, the user can wire this themselves.
If you do this Prop I-64 then could the Prop II have:
(I don't know the impact on lead time and where you are up to, but presume you are into the hub from your postings)
* More cogs (16) at the expense of some hub ram and rom? (I still see this as an issue, especially with external memory and microSD cards)
* More than 64 pins so that the SDRAM or SRAM could be used without impacting the 64 I/O pins. I guess what I am asking for is a hub memory controller accessed by a·cog to hub RD/WR style command.
(We are stuck with SMT so the package is not so much of a problem as long as someone places it on a daughterboard)
Alternately, could 8 older Prop I cogs (smaller footprint than the Prop II cogs)·be added to the Prop II with a slower hub access?
▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
Links to other interesting threads:
· Prop Tools under Development or Completed (Index)
· Emulators (Micros eg Altair, and Terminals eg VT100) - index
· Search the Propeller forums (via Google)
My cruising website is: ·www.bluemagic.biz
1) price (should not be more than 1.5x current prop)
2) package (SMD soldering of 0.05" is fine, 1mm is doable, smaller is painful - at least for me) PLCC84 would be nice [noparse]:)[/noparse]
Frankly, I would also love a 28 pin dip version of the prop, say
P0-P15, P24-P31, -RST, OSCIN, Vdd, Vss
▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
www.mikronauts.com - a new blog about microcontrollers
@ Chip: I agree with many people's opinion of making RAM expansion very easy, but given the current economy and the cost of getting the Prop B to market, I think this is a decision that requires some market analysis. How much you'd have to sell it for, how much the Prop 2 would sell for and see if there would be enough of a valley between the Prop 1 and Prop 2 to warrent the Prop B. The worst would be seeing· decent sales at it's unveiling only to see it drop to nothing once the Prop 2 is out. Hobbyists will always say they want more options but it's volume sales over time that make or break a product.
Back @ All: rather than just answering if you want 64 I/O pins seriously consider if you would buy (and even more important build products around) the Prop B once the Prop 2 is out. Cole and Cluso99 have the right idea in thier answers, they're not just considering the # of I/O pins but applications where it's preferable that the chip has lower power.
▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
Paul Baker
Post Edited (Paul Baker) : 1/30/2009 4:24:32 AM GMT
All I care about is that it be hand-solderable by mere mortals. PLCC, SOJ, anything with leads with 1mm or greater spacing please
(taking out crystal ball, talking qty.1 US pricing)
Prop 1 is $13
Prop 1-64 at $15 would probably sell like hotcakes, would probably sell ok at $18, but would not sell above that
Prop 2 at $20 would sell well, would sell ok at $25, would move very slowly at $30, and higher would be disaster
(putting away crystal ball)
Depends on the project. 64 I/O and low power would be a winner for many designs where Prop I might now need an AVR or two, or SPI peripherals.
Prop 2 will be wonderful, slice bread, etc, but Prop 1-64 will be "good enough" for a fair set of problems.
The real question is... how many units does parallax need to ammortize the 80k over?
▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
www.mikronauts.com - a new blog about microcontrollers
I2C and SPI ram is far too slow to use as a frame buffer
(unless you hooked up eight in parallel, then theoretically you could stream-read fast enough for NTSC/PAL video)
▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
www.mikronauts.com - a new blog about microcontrollers
Post Edited (Bill Henning) : 1/30/2009 4:39:48 AM GMT
I for one, would take 4 Prop B Proto boards at $50 each if they are anything like the protoboards we have now. Those things are very handy.
Here's where I see great advantages to Prop B:
1. Connection to RAM.
2. More pins to connect high speed buses in multiprop designs.
3. Maybe eliminate the need for some multiprop design(how many times have people run out of cogs only to find that they could double up on tasks/cog?)
4. Downsizing/simplifying current designs because ram #1 ...Like the Extreme Memory expansion, OpenStomp, etc.
5. No learning curve for those that just need more pins or ram, not more processing power(I for one, have not done assembly on a pipelined processor and tried to calculate clock ticks for loops)
I for one, after thinking about it, agree with cluzo's "I guess what I am asking for is a hub memory controller accessed by a cog to hub RD/WR style command." in Prop II.
It would open up the possibilities of the chip to be used in many industrial designs where ARM and MIPS are common right now because they have a descent processing power and access to lots of SDRAM ie: Cable Routers and other network devices.
It sure would be simpler for those with large memory needs to keep things coherent than 3 levels of memory. I like simple. I like the propeller.
I don't know if it is way late to be bringing up such things in the design cycle of the Prop II, but you probably have thought that through already.
Just another 10 bits worth,
Doug
Please stick to your original plan. The memory controller is a right idea at the right time.
Do you need help finalizing the design? Your design seems to be getting away with being all things to all people.
Please don't design by committee - KISS principle is best.
I love your work.
▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
JMH
Totally agree! But it is barely possible, and the only way I could see doing it with SPI ram for any sort of screen buffer
Having an additional 32 bits of fast I/O certainly does open possibilities...
▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
www.mikronauts.com - a new blog about microcontrollers
Edit: In my Prop6502 laptop, you could map sections of 6502 RAM to go to the Propeller's hub RAM instead of the external SRAM chip; this would be like that, but in reverse.
Edit 2: Or would it be cleaner to have an instruction, like RDBYTE but not the same code, for reading external RAM?
Post Edited (Dennis Ferron) : 1/30/2009 5:48:02 AM GMT
For the Prop I-64, there are cheapish 4Mb-64Mbit SPI Flash available with 2 pin fast reads (W25X32 from Digikey about $2.80). SRAM in 128KB, 512KB (32DIP AS6C1008, AS6C4008 about $4, $9) and 2MByte (the 2MB is v.low power and battery backed internally 32DIP· M48Z2M1V about $150 from Digikey - ouch) as well as Chip's SDRAM 32MByte. These can all be easily interfaced with the extra pins.
I know no-one wants to here this, but IMHO, it would relieve some of the pressure on the Prop II so that we could get some extra features like the SRAM/SDRAM interface as a pseudo hub access instruction. Chip, if you do, please add more pins for this interface (i.e. plus 64 I/O), and pretty please... more cogs (new or old style) because this chip is going to fly. With the Prop I-64, the Prop II can withstand a higher price so·you could have the extra die space required.
@Quantum: I am well on the way with the layout - hope to send it away for mfg before I get tied up next week. :-)
@Dennis: The SDRAM only uses 29/30 pins as it is multiplexed RAS/CAS·(for bytewide). For SRAM 4MByte can be addressed with 32 pins (or 8MByte if CE tied low). Hub access uses 32 bit addresses (bytewise), just the extra bits are ignored (unsure whether it wraps or not).
▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
Links to other interesting threads:
· Prop Tools under Development or Completed (Index)
· Emulators (Micros eg Altair, and Terminals eg VT100) - index
· Search the Propeller forums (via Google)
My cruising website is: ·www.bluemagic.biz
Post Edited (Cluso99) : 1/30/2009 6:24:26 AM GMT
This SDRAM is attractive because of its density/price, but random-access performance is pretty lousy due to all the RAS/CAS and delay cycles required before data comes out. Once is starts coming out, though, you can get a big stream pretty quickly. Now I·have a better understanding of·just why Pentiums must have large internal caches to get high performance. A cache is quite a silicon commitment and I don't think it's the kind of thing that belongs in a Propeller chip.
▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
Chip Gracey
Parallax, Inc.
And do not forget the 64 IOs Propeller I!
We just need access to more memory and if you can handle both SRAM and SDRAM (select one or the other when initialising the controller) it can be initialised by a cog and left to run. There would be an advantage to be able have the hub load a block of SDRAM into the hub (or cog?) using the controller to do an automatic burst mode.
▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
Links to other interesting threads:
· Prop Tools under Development or Completed (Index)
· Emulators (Micros eg Altair, and Terminals eg VT100) - index
· Search the Propeller forums (via Google)
My cruising website is: ·www.bluemagic.biz
Using RDBYTE/RDWORD you could even allow for a 16 bit data bus
It would also be very nice to have an SRAM mode, 10ns SRAMS are readily available at fairly decent prices, with a bit more circuitry it would allow for say a 16 cycle hub like shared external memory
Combine that with a 16 bit external data bus, and there would be potentially 80x2 = 160MB/sec memory bandwidth (combined, for all cogs, ie 20MB/sec per cog, same bandwidth as current hub memory bandwidth on Prop 1!)
I think something like:
B0-B15 = data bus
B16-B27 = 12 bit address bus
B28 = -ALE / -RAS (as ALE, latch B16-B27 into external latches, for more address lines, also latch B0-B15)
B29 = RD
B30 = WR_LO
B31 = WR_HI
(I know, we'd have to steal a pin from Port A for CAS, unless of course you had dedicated -RAS/-CAS/-RD/-WRL/-WRH pins outside of the normal port B, in which case B28-B31 could be used for "bank" or additional address bits)
The only down side is an additional clock required to latch the upper part of the address when it changes.
Food for thought...
actually, it may be better to have the memory window for XRAM to be 24 cycles - that would allow for strobing a new high address for each cogs cycle, AND it would allow for double reads/writes needed to support RDLONG and WRLONG
160MHz/24 cycles = 6.66M cog-accesses (per cog) per second, using LONG's that would be 26.6MB/sec bandwidth, greater than current hub bandwidth
20 cycle windows may be possible, and that would be even better:
160MHz/20 cycles = 8M cog accesses (per cog) per second, using longs it would be 32MB/sec bandwidth per cog
1024x768x8 bit VGA needs about 48-60MB/sec to feed... two cogs would have enough bandwidth!
▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
www.mikronauts.com - a new blog about microcontrollers
Post Edited (Bill Henning) : 1/30/2009 3:30:49 PM GMT
Re: Cache
Seems to me, the design of the Propeller is kind of like a CPU with cache and such already. If there is external RAM, and if there are limits on it that exceed HUB limits, then a COG or two could be managing that, leaving the HUB memory to be essentially a cache anyway, particularly where LMM kinds of programs are concerned.
▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
Propeller Wiki: Share the coolness!
Chat in real time with other Propellerheads on IRC #propeller @ freenode.net
Safety Tip: Life is as good as YOU think it is!
I would really like to see it personally, but I am not going to pay the $80k, but as I said, I would pay $50 for a Prob B USB ProtoBoard, in fact take 4 of them.
Re: Cache,
Yes it is currently like that. With external ram + hub ram + cog ram, there is more to keep coherent which adds complexity, burns cycles, etc. I really like the cog ram plus ram controller for hub idea for SRAM, but as Chip was saying for SDRAM, there would need to be some kind of cache, which would kind of mess up determinism. Yes, it is deterministic, but it depends on the state of the cache how far you are reaching to a different address....
When it comes to memory architectures, my favorite is UMA like in the SGI O2 which is somewhat like the current prop.
http://www.futuretech.blinkenlights.nl/o2arch.html
http://en.wikipedia.org/wiki/SGI_O2
Big memory has some definite advantages when reaching into other markets. I for one would like to see the propeller reach into markets that are now dominated by MIPS and ARM, and most of these have big ram.