Leon - just looked at your GIF - presume the gif output is slightly off as the tracks on the bottom of connector 7 has underside tracks close to the pads. ALso noted there is silk screen (yellow) diagonal lines across IC6 to IC2 over the solder pads. Seems to be tracks (red) around most smt caps/res (presume different layer). IC1 lower left has "Z" bend in track. C14 has blue "X" over one pad, same on upper pads IC2. Suggest you shorten the track to the xtal pin from the prop. Just a quick look - hope this helps.
Can you get a decoupling cap close to the prop power pins?? And IC2??
All the clearances are OK, I set the design rules to 8/8 mils. The tracks might look close to some of the pads, but the actual pad is the inner grey ring, the blue ring round it is the solder mask. There is actually plenty of clearance, although I wouldn't take them that close if I was routing manually. I'll be routing all the ground and power connections manually, as well as the other critical nets, when I do the proper layout. Those two diagonal yellow lines are unrouted nets. The tracks from the capacitors are connections to the ground and power planes.
Leon
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Amateur radio callsign: G1HSM
Suzuki SV1000S motorcycle
Leon, I posted a message in heaters CPM thread about making a CPLD/SRAM board for his 8080 emulator and he mentioned that you were working on something similar. I include my post below. What do you think? Is this a practical idea using the CPLD you have used for this project?
I took a quick look at the price of CPLD's and RAM with the following results:
A CPLD with 48 I/O's costs less than $10.00. A 1/2/4 meg RAM (128K/256K/512Kx8) costs less than $5.00.
With that CPLD and RAM we should be able to build a memory board that uses 12 pins to access 128/256/512KB of ram and speed up emulation.
The CPLD would implement the following commands:
Load 8 bits from Prop to address register low byte.
Load 8 bits from Prop to address register mid byte.
Load 8 bits from Prop to address register high byte.
Load 8 bits from Prop to data register low byte.
Load 8 bits from Prop to data register mid byte.
Load 8 bits from Prop to data register high byte.
Increment address counter.
Increment data counter.
Read instruction from RAM to Prop.
Write instruction from Prop to RAM.
Read data from RAM to Prop.
Write data from Prop to RAM.
by the way, the thing you're talking about is pretty much Andre's HX512, ok $60 is more than $15, but it's pre-built, and plugs into Hydra and Hybrids.
Comments
Can you get a decoupling cap close to the prop power pins?? And IC2??
Post Edited (Cluso99) : 11/10/2008 4:13:52 PM GMT
Leon
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Amateur radio callsign: G1HSM
Suzuki SV1000S motorcycle
Leon
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Amateur radio callsign: G1HSM
Suzuki SV1000S motorcycle
Post Edited (Leon) : 11/10/2008 7:01:54 PM GMT
I took a quick look at the price of CPLD's and RAM with the following results:
A CPLD with 48 I/O's costs less than $10.00. A 1/2/4 meg RAM (128K/256K/512Kx8) costs less than $5.00.
With that CPLD and RAM we should be able to build a memory board that uses 12 pins to access 128/256/512KB of ram and speed up emulation.
The CPLD would implement the following commands:
Load 8 bits from Prop to address register low byte.
Load 8 bits from Prop to address register mid byte.
Load 8 bits from Prop to address register high byte.
Load 8 bits from Prop to data register low byte.
Load 8 bits from Prop to data register mid byte.
Load 8 bits from Prop to data register high byte.
Increment address counter.
Increment data counter.
Read instruction from RAM to Prop.
Write instruction from Prop to RAM.
Read data from RAM to Prop.
Write data from Prop to RAM.
Leon
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Amateur radio callsign: G1HSM
Suzuki SV1000S motorcycle
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--Steve
Post Edited (jazzed) : 2/24/2009 8:20:01 PM GMT
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JMH