Yes. But >LMM is not true Parallel procesing.
In LMM you must wait to read HUB mem.
It is semi parallel. It decrease COG´s speed to standard linear CPU
▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔ Nothing is impossible, there are only different degrees of difficulty.
Beau Schwabe: Thanks for taking the time to look into MRAM. I had no idea about layer requirements.
I did wonder about the matching of physical construction issues with layout packages that probably don't have all the fabrication details. You've given me a better insight that world.
I don't expect that the speed restriction would impact at the Prop's clock-rate. And using older tech fabs is desirable too I think. A lot less commercial pressure.
Sapieha said...
"" All Cogs running LMM do run in parallel but the performance of each Cog does drop ""
Yes it is wery big decrease in Cogs performance!
Sapieha said...
I wanting a Very power full parallel procesing Propeller not linear.
In 8 COG´s Propeller You mus want 16 clocks to read one LMM instruction.
I think that what you are looking for is so fundamentally different to what the Propeller architecture is that it's not going to happen. While LMM isn't true parallel processing in the sense that any access to Hub must block, for most applications that seems good enough and amounts to what I would consider parallel processing.
To me it's all a question of latency in doing what it must do and I haven't seen any particular problems in that with the Propeller although I would say that really does depend on application.
It was only My ideas.
This is not My but Chip construct it and I am familar with it.
My only point is Propeller Is parallel procesing micro and very handy in it.
But if Chip construct Ver II it is for att it wil be beter and my ideas had it in mind.
▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔ Nothing is impossible, there are only different degrees of difficulty.
I don't see LMM is such a big downgrade in performance really. BTW, What is the current MIPS expectation for a single LMM Cog?
Yes you can consider LMM full blown SMP. I can say this simply because one Cog can not steal Hub time/accesses from another Cog, unlike a multi-threaded CPU. And completely non-linear I might add.
And yes, I meant low power consumption. The Cell is a bit of a space heater.
You're missing a point also. To go down your path the instruction set would need a huge overhaul to increase the register space, or to shift to registers + memory addressing. Then the Cogs get all bloated with all this extra ram and push the Hub aside.
Ah, Hippy posted one answer I was after. The LMM achieves 5 MIPS! That's amazing really. Sapieha: You're getting picky saying that 5 MIPS is slow compared to 20 MIPS.
Do ProII has instructions to multiply into machine code?
Are numbers 16bit or 32bit?
has 64 outlets / tickets can be parallel port of 8 or 16 bit LCD without using the rest of the 64?
I like the idea of instructions per cycle relog.
Will also with the memory accesses the hub?
Perhaps in this thread are already answered my questions, but I am wrong with the English.
Sorry for my English potato
hal2000 said...
Do ProII has instructions to multiply into machine code?
Are numbers 16bit or 32bit?
has 64 outlets / tickets can be parallel port of 8 or 16 bit LCD without using the rest of the 64?
Will also with the memory accesses the hub?
1: I believe so. Chip has said that a multiply instruction is planned. I can't find the quote though.
2: ??? The Prop has always been 32 bit. Or do you mean Hub address range? That's looking to be upped to 32 bit.
3: You can already specify bit by bit which pins are driven.
4: No, Cog addressing is separate from Hub addressing. However, LMM provides what you want I think.
Comments
Yes. But >LMM is not true Parallel procesing.
In LMM you must wait to read HUB mem.
It is semi parallel. It decrease COG´s speed to standard linear CPU
▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
Nothing is impossible, there are only different degrees of difficulty.
Sapieha
I did wonder about the matching of physical construction issues with layout packages that probably don't have all the fabrication details. You've given me a better insight that world.
I don't expect that the speed restriction would impact at the Prop's clock-rate. And using older tech fabs is desirable too I think. A lot less commercial pressure.
Evan
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Propeller Wiki: Share the coolness!
Chat in real time with other Propellerheads on IRC #propeller @ freenode.net
You said.
"" Get a grip! This is a low power device. ""
Yes to low power consumption. No to low power procesing.
What You mean "" You are wanting a Cell chip "
I wanting a Very power full parallel procesing Propeller not linear.
In 8 COG´s Propeller You mus want 16 clocks to read one LMM instruction.
You said "" Get a grip ""
▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
Nothing is impossible, there are only different degrees of difficulty.
Sapieha
I think that what you are looking for is so fundamentally different to what the Propeller architecture is that it's not going to happen. While LMM isn't true parallel processing in the sense that any access to Hub must block, for most applications that seems good enough and amounts to what I would consider parallel processing.
To me it's all a question of latency in doing what it must do and I haven't seen any particular problems in that with the Propeller although I would say that really does depend on application.
It was only My ideas.
This is not My but Chip construct it and I am familar with it.
My only point is Propeller Is parallel procesing micro and very handy in it.
But if Chip construct Ver II it is for att it wil be beter and my ideas had it in mind.
▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
Nothing is impossible, there are only different degrees of difficulty.
Sapieha
Yes you can consider LMM full blown SMP. I can say this simply because one Cog can not steal Hub time/accesses from another Cog, unlike a multi-threaded CPU. And completely non-linear I might add.
And yes, I meant low power consumption. The Cell is a bit of a space heater.
Evan
Thanks fo link.
But Cell and it I spoken is not be same.
You totaly mised point in my ideas.
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Nothing is impossible, there are only different degrees of difficulty.
Sapieha
Is the Hub of any value to you at all?
You said.
"" Is the Hub of any value to you at all? ""
Yes. Very big value
▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
Nothing is impossible, there are only different degrees of difficulty.
Sapieha
Are numbers 16bit or 32bit?
has 64 outlets / tickets can be parallel port of 8 or 16 bit LCD without using the rest of the 64?
I like the idea of instructions per cycle relog.
Will also with the memory accesses the hub?
Perhaps in this thread are already answered my questions, but I am wrong with the English.
Sorry for my English potato
It just feels 'wrong' to me to have to clear a register and write that or to define a zero constant to use.
Edit : Found a workround ...
CON ZRO = $1F7
wrlong ZRO,xxxx
This uses DIRB which most people won't be using in a Mk 1 program.
Post Edited (hippy) : 8/30/2008 9:48:33 PM GMT
Agreed
2: ??? The Prop has always been 32 bit. Or do you mean Hub address range? That's looking to be upped to 32 bit.
3: You can already specify bit by bit which pins are driven.
4: No, Cog addressing is separate from Hub addressing. However, LMM provides what you want I think.
Evan