More Prop II info..!?!
LewisD
Posts: 29
Hi Everyone,
I Have just had time to watch the seven YouTube Videos of Chips Interview...
I Think I found a few NEW nuggets of information about the Prop II .
Maybe they have been reported on already but they did not make it into the Prop II wiki.
propeller.wikispaces.com/Propeller+II
Watch this video (3 of 7) from minute 4:50 to about 5:30.
www.youtube.com/watch?v=DXbMBOzr46Q&feature=related
Not a lot,but what I heard was that every I/O pin will have an iterative A/D ( no bit depth mentioned... I think)
and a comparator that can be used for USB...
Maybe someone with better ears can get more from the clip.
I do hope Ethernet will also be possible, Even 10Mbs would be great.
LewisD <--- Patiently waiting for Prop II
(I fixed the broken Links)
Post Edited (LewisD) : 8/21/2008 10:09:01 PM GMT
I Have just had time to watch the seven YouTube Videos of Chips Interview...
I Think I found a few NEW nuggets of information about the Prop II .
Maybe they have been reported on already but they did not make it into the Prop II wiki.
propeller.wikispaces.com/Propeller+II
Watch this video (3 of 7) from minute 4:50 to about 5:30.
www.youtube.com/watch?v=DXbMBOzr46Q&feature=related
Not a lot,but what I heard was that every I/O pin will have an iterative A/D ( no bit depth mentioned... I think)
and a comparator that can be used for USB...
Maybe someone with better ears can get more from the clip.
I do hope Ethernet will also be possible, Even 10Mbs would be great.
LewisD <--- Patiently waiting for Prop II
(I fixed the broken Links)
Post Edited (LewisD) : 8/21/2008 10:09:01 PM GMT
Comments
A Comparator function would be a relatively easy implementation of the ADC.
Yes, there will be a Sigma-Delta Style ADC on each pin that will work much the same way the Sigma-Delta ADC object works.
The main difference is that the feedback resistor and capacitors that connect to either rail will be part of the I/O pin itself.
The 'depth' will be a function of how much time you want to·spend sampling the·pin.
Attached is a screen shot of one of the IO_PAD's... it includes ESD protection along with the Sigma-Delta ADC components, as well as driver transistors for the IO configured as an Output.
▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
Beau Schwabe
IC Layout Engineer
Parallax, Inc.
▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
The Pi Guy
I stopped to watch the whole interview this time. That's even cooler. Parallax is clearly a nice place to work. [noparse]:)[/noparse]
Chip, you need to get a grip on what's normal me thinks ... talking about IC design as if every small design shop is doing it these days. If I'm not mistaken, the FPGA craze and it's masked versions, is meant to take up a lot of that market. Or, one is expected to use one of the myriad of controllers being put out by the corporates.
You've really leaped ahead with the Prop.
Evan
Indeed a great place to work!!!
Floorplan:
1 - PMOS CAPS
2 - NMOS CAPS
3 - RESISTOR BANK
4 - control logic for the Sigma delta, and I/O pin
5 - ESD protection
6 - level shifters and some glue-logic
7 - PMOS transistor PAD driver
8 - NMOS transistor PAD driver
9 - wire bond PAD landing
Keep in mind that the caps, resistors, and ESD structures are all routed in the first layer of metal (BLUE color)
This is a big deal, since that means that The remaining Metal layers (4 of them) can be used for power routing over these structures.
Only one layer here is shown (Red horizontal straps)
▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
Beau Schwabe
IC Layout Engineer
Parallax, Inc.
Post Edited (Beau Schwabe (Parallax)) : 8/23/2008 9:58:47 PM GMT
▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
The Pi Guy
"Can you give us any idea of any changes to the counters or is that still under wraps/being developed?" - Until Chip is willing to divulge a new important aspect, my lips are sealed.· I don't know the inter workings of how the propeller IDE would handle the differences, other than to the user it would simply be another·command ( <-- I think) used to set the pin up as an ADC verses how the·IDE·currently works.·
▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
Beau Schwabe
IC Layout Engineer
Parallax, Inc.
The neighboring output could be routed via a resistor since there is no need for high current when driving the converter. But then it couldn't be used as an input itself.
Ah, that's it, there is no need for a tough driver in the converter at all! The driver can be safely hidden away behind it's high value resistor. Nice.
Man, what happened to the days of expensive complex A/D converters? It's impressive what can be saved with some thought.
Evan
"Looking at the layout there is obviously serious sizing issues dealing with the final stage output transistors" - actually not really... many of the individual gates on those transistors are tied back to Vdd or Vss.... This creates your reverse bias diode on the I/O pins.·· Only a few gates are required to be active for driving these transistors.· The power routing is adequately sized to handle at least 40mA.· ... Same as the current Propeller design.
▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
Beau Schwabe
IC Layout Engineer
Parallax, Inc.
·
Attached is a closer view with vertical metals turned off.· You can see where some fingers (green-horizontal· - almost covered by Vss contacts)·are tied to Vss (bluish layer - Metal 1) while others are active (next metal up·- Metal 2·- red color)
·
▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
Beau Schwabe
IC Layout Engineer
Parallax, Inc.
▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
The Pi Guy
Soon, but that doesn't mean a Prop II release yet... just final testing for us with the layout blocks that we currently have to date, and to make sure everything is in check with them before we proceed with the logic that ties all of the current blocks together.
▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
Beau Schwabe
IC Layout Engineer
Parallax, Inc.
Post Edited (Beau Schwabe (Parallax)) : 8/25/2008 5:01:47 AM GMT
▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
Paul Baker
Propeller Applications Engineer
Parallax, Inc.
The waitvid instruction is a very useful "serializer" ... not having the opposite "deserializer" is kind of like going stag to the prom. Having a deserializer could make some wonderful things possible. I know how to use multiple cogs to achieve the same result, but it sure is a waste of computing power.
▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
--Steve
▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
Chip Gracey
Parallax, Inc.
I'm no modulation expert, but it seems that some obvious other needs in are: PAM (100Mb Ethernet), FHSS (Bluetooth), DSSS (802.11b), OFDM (ADSL,802.11a/g,802.16). Trying to support 8b/10b for Gigabit Ethernet is probably absurd.
With NRZ SONET is possible, but the problem becomes clock recovery. SONET OC1 is about 51Mbps and seems doable if you have a 160Mhz clock. OC3 at 155Mbps is likely a bit high. Finding a generic way to serve the different "chronoses" would be good but not likely (syn, isosyn, plesiosyn, etc...).
Some of this might depend on what royalty based 3rd party FPGA IP is available. It might take a huge effort to do it alone.
In any event, SERDES ability can help score networking company design wins, but getting something out the door quickly to serve your current loyal and hungry customer base would be more wonderful [noparse]:)[/noparse]. You could always add more complicated features later.
Thanks
▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
--Steve
·
·
As far as the high speed SerDes, I will probably be proven wrong, but ...· At National Semiconductor I was involved with the high speed communications division using SerDes chips that were completely dedicated to handle and process the high speed internet bandwidth.· You can most likely achieve 10/100, but I doubt Gigabit speeds can be reached without dedicating at least half or more of your cogs running in stepped phase increments to one another.
·
▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
Beau Schwabe
IC Layout Engineer
Parallax, Inc.
Something like serial data and I2C will work regardless of clock rate, albeit much slower.
Am I correct in assuming that different protocols require certain bandwidth? Or would it not matter?
-Parsko
You said.
"" Yes, I've been thinking about this, too. I just need to narrow down what kinds of demodulation we should support. Manchester and NRZ come to mind, but are there others? ""
I one of my threds I have proposo to deserializer.
It is maybe one off interest ??
▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
Nothing is impossible, there are only different degrees of difficulty.
Sapieha
▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
Chip Gracey
Parallax, Inc.
Thanks for replay.
My post is in that thred.
It is first post in it.
http://forums.parallax.com/forums/default.aspx?f=25&p=1&m=212396
▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
Nothing is impossible, there are only different degrees of difficulty.
Sapieha
Going the other way, for example, the Prop I's video circuitry knows nothing about Manchester code or PWM, but it can be made to generate both at high speeds. The counters were never designed to be RF mixers, either, but they can be configured to perform that task. This is because the hardware was made general enough for software to virtualize these higher-level functions.
Also, it may be helpful to think of deserailization as n-bits-per-clock, rather than just 1-bit-per-clock, in the same way that the video circuitry works with multiple pins in parallel, but for packing data, rather than unpacking it (and without the LUT). This would allow fast video capture to become a reality.
-Phil
▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
'Still some PropSTICK Kit bare PCBs left!
Given big enough buffers and high enough sample rate, you can do anything.
Some type of coding would be great if it was "cheap" to do. Manchester is fine for 10BaseT and may be useful for little network connections. Just having a serial-parallel shift register and latch (which can be NRZ or whatever ... NRZI+4b/5b encoding app= 100BaseTX/FX) would buy more performance functionality than we have now or would have in Prop II without it.
▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
--Steve
How many instructions per second could we expect from the prop II, both asm and spin?
What would be the reccomended operating frequency, and would the 5MHZ crystal on
current props work (with mabye PLL32X)??
About how much would prop II/protoboard cost?
The built in A/D's are awesome! This will simplify many of my projects, no more
external A/D chips. Would they be eight bit A/D's though?
Prop II is probably overkill for anything that I throw at it (prop I already is), but I still look forward
to getting one.
Parallax Rocks!
Kevin
The Prop II will have a system clock up to 160MHz, but with a one instruction per clock pipeline in each of 16 cogs.· You figure out the numbers.
We don't know how different the Spin interpreter will be on the Prop II, but most of it should be the same so figure that the Spin execution speed will have the same Prop I : Prop II ratio most of the time.
Nobody knows how much it will cost or how much a Protoboard with it will cost.· I suspect that that cost won't be too much different from the Prop I.· The cost of making a chip is roughly proportional to its area and the size and number of pins in its package, but a lot of the cost is R & D and marketing / sales.
I don't know how the built-in crystal oscillator will work.· It might still use a 5MHz crystal with a PLL32x or it might use a 10MHz crystal with a PLL16x.· There are reasons for doing both.