ADC smartpin help needed

CRST1CRST1 Posts: 101
edited 2019-12-08 - 03:32:59 in Propeller 2
Ok all you guys out there smarter than me, that would probably be everyone.

I've gotten the counter and pwm pin modes working now with help.
Now I need some adc pins. Again confused about the descriptions.
The P2 document shows the wrpin instruction D operand as
D/# = %AAAA_BBBB_FFF_PPPPPPPPPPPPP_TT_MMMMM_0
The Sinc3 filtering mode shows example:
To begin SINC3 filtering:

WRPIN ##%100011_00000000_00_11000_0,#adcpin 'configure ADC+filter pin(s)
WXPIN #%10_0111,#adcpin 'SINC3 filtering at 128 clocks
DIRH #adcpin 'enable smart pin(s)
I understand the _00_11000_0,#adcpin part of it but the PPPPPPPPPPPPP part I am confused on
Its showing %100011_00000000_ and there are 14 bits. The P's has only 13 bits.
I used the example to set up the pin but I am getting eratic values.
I've been looking at the chart for the P values but its not making sense. especially with the extra bit.
I tried grounding the pin and figured it should read 0 and hooked to 3.3 it should be maxed out.
I only reading the pin if the IN is high.

Can someone explain how the example sets up the pin for adc filtering?

Is the first 1 part of the %FFF part?
Meaning A and B, B and what does this mean
%FFF: 'A' and 'B' input logic/filtering (after 'A' and 'B' input selectors)
000 = A, B (default)
001 = A AND B, B
010 = A OR B, B
011 = A XOR B, B
100 = A, B, both filtered using global filt0 settings
101 = A, B, both filtered using global filt1 settings
110 = A, B, both filtered using global filt2 settings
111 = A, B, both filtered using global filt3 settings
«1

Comments

  • Huh, you're right, it looks like Chip has one too many bits. The group of 8 zeros should be 7.

    Have a read of my links if you haven't anyway, you should find them helpful - https://forums.parallax.com/discussion/comment/1483529/#Comment_1483529
    You'll see I've divided the %P's up a little more than Chip does.

    That %FFF filter is not for ADC. That's just a really basic three sample unanimous voting deglitcher for digital inputs.

  • Ok great, I'll try that and see.
    Thanks
  • So I made it WRPIN ##%100_011_0000000_00_11000_0,#adcpin and still eratic reading.
    Is that the correct way with the ##%
  • Regarding understanding it all. The software portion of the ADC SINCx "filtering" modes - with full resolution output, has to apply a differentiation to the read Z values before it becomes an ordinary PCM sample. And in the case of SINC3 it's a double diff. Here's a block diagram of a SINC3 where you see there is three accumulators followed by three differentiators. The accumulators operate at the bit-clock, or faster, sample rate, while the differentiators operate at the PCM (decimation) sample rate. So it can probably be categorised as a resampling circuit too.
    appnote.tsa002.png

    The performance appears magical at first, then once you get to grips with the simplicity of implementation the maths behind it becomes mind boggling. If you ever get to grips with that then get yourself off to university.

    Anyway, in the prop2, the accumulators and the first differentiator are in the smartpin. The remaining diffs are easy to perform in software.

    The ADC frontend and bitstream modulator hardware in the prop2 is approximately like this
    Prop2_ADC_functional.png

    Further theoretical reading at http://www.ti.com/lit/an/slyt423a/slyt423a.pdf

    600 x 176 - 11K
    1150 x 383 - 12K
  • evanhevanh Posts: 8,975
    edited 2019-12-08 - 04:33:31
    CRST1 wrote: »
    So I made it WRPIN ##%100_011_0000000_00_11000_0,#adcpin and still eratic reading.
    Is that the correct way with the ##%

    Yep, that's correct. Yeah, sorry, spent too long writing the follow up post. You have to apply a second diff operation for SINC3 compared with SINC2. So it becomes
           SUB     x,diff1
           ADD     diff1,x
           SUB     x,diff2
           ADD     diff2,x
    

    EDIT: Or is that what you're already doing?

  • CRST1CRST1 Posts: 101
    edited 2019-12-08 - 04:43:26
    I tried this:
    asm
        dirl #17
        wrpin   ##%100011_0000000_00_11000_0, #17
        wxpin   #%10_0111,  #17
        dirh #17
    
    
      endasm
    
    And then
    repeat
      if ina[17] == 1
        asm
          rdpin  x1,  #17
          sub    x1,  diff1
          add    diff1,  x1
          sub    x1,  diff1a
          add    diff1a,  x1
          shr    x1,  #7
        endasm
    

    Now I get -60765106 constant with voltage or ground on pin.
    Edit: Was using the wrong var. The value is still erratic, doesn't chang when connected grnd or 3.3.
  • evanhevanh Posts: 8,975
    edited 2019-12-08 - 04:47:06
    CRST1 wrote: »
    Edit: Was using the wrong var. The value is still erratic, doesn't chang when connected grnd or 3.3.
    You're going to get huge numbers. What value is it?
  • CRST1CRST1 Posts: 101
    edited 2019-12-08 - 05:02:50
    evanh wrote: »
    You're going to get huge numbers. What value is it?

    Value? You mean a long? I have x1 as a var in the main pub.
    PUB Main | diff1, diff1a, x1

    What do you mean huge numbers? What kind of values will it be?
    Got me confused again. not hard to do!!

    What kind of value would 0 volts give and 3.3 give?
  • evanhevanh Posts: 8,975
    edited 2019-12-08 - 05:12:55
    The reading. Okay, a quick calc tells me not as big as thought. 3.3 volts (VIO) as input voltage should be a value of about 13,600 after the SHR #7. And 0 volts (GIO) should be about 2800.

    I don't usally bother with the SHR at that stage so my PCM samples are somewhat larger. EDIT: And I have been known to experiment with higher than 512 clocks per decimation.

  • I guess you mean value being read.
    It comes in like this
    830923
    32263999
    934087
    33306487
    343213
    33365330
    33057537
    101473
    707636
    32542766
    926584
    33398736
    33068055
    273323
    33254675
    668278
    97071
    33008946
    134034
    33526339
    33010131
    1224762
    32292196
    572744
    33364783
    406089
    33380127
    33493678
    283516
    33441355
    33474806
    33457944
    33486328
    33091032
    974174
    32898719
    662870
    32973321
    283069
    33215130
    33455670
    33436166
    529822
    642179
    32758184
    33314410
    662240
    32478841
    1254542
    33261536
    3306131
    
  • Hmm, looks like the diffs aren't working. That's output of x1 right?
  • Yes
  • Double hmm ... 33,554,432 is largest possible value after the SHR. Funnily you have lots of values just below that. It suggests you are getting negatives, but it's all unsigned up to the SHR so I don't see how it can go negative.
  • If I removed the SHR #7 it did have a lot of negitives.
  • evanhevanh Posts: 8,975
    edited 2019-12-08 - 05:36:30
    Oh, those diff variables have to persist. That's called "static" in C. I don't know how spin deals with specifying persistent variables. You probably need to define them at beginning of whole program.

  • Well its late here so if you have any suggestions I try again tomorrow.
    Thank you for the help.
  • It'll be the diff's, they'll be stacked variables of something. That needs changed to globals or some type that is persistent.

  • If you are interested in making DC measurements more than AC, I would just use the SINC2 sampling mode that does all the work for you. You configure it and then just read the samples via RDPIN.
  • cgracey wrote: »
    If you are interested in making DC measurements more than AC, I would just use the SINC2 sampling mode that does all the work for you. You configure it and then just read the samples via RDPIN.

    I tried the plain sampling mode and it works like I thought it should.
    I guess I don't have a clue about what the filtering modes are about. I figured they would just be a more stable reading to filter out any noise in the signal. I guess my head can't absorb all the information.

    Maybe in time someone will write a tutorial on how to use the smart pins like the counters on the P1.

    Thanks, I think the sampling mode will work for now.
  • You just have to make those diff variables into persistent storage. It's important that they track prior decimation values for as long as you want to take samples for. I suspect the way you've defined those diffs will be on the stack which only lasts as long as that function is running.

    I don't really know much about the Spin language so someone else will have to give advise on how to make them persistent.

  • evanh wrote: »
    You just have to make those diff variables into persistent storage.

    Yeh I haven't gotten into the persistent stuff about variables so far. Never needed to.
    How about you writing the document about all these smart pin modes!!! haha!!
    You're links do help some but I'm still dense until I see it work. So far I've got the counting, triangle PWM and this ADC figured far enough to start implementing it for this 4D systems display dashboard in my mustang.
    Has to read tach, speed and fuel flow pulses, analog fuel level, oil press, temp and oxygen sensors and output PWM for rgb led lights.

    Thanks again "evanh" and "cgracey" and all who responded.
  • evanh wrote: »

    The ADC frontend and bitstream modulator hardware in the prop2 is approximately like this
    Prop2_ADC_functional.png

    Evanh -- Let me ask one more question since you put up this diagram.
    will setting the different resistors in combination with the caps do a hardware filter of different values? I guessing because it is R-C type of filter.
  • CRST1 wrote: »
    evanh wrote: »

    The ADC frontend and bitstream modulator hardware in the prop2 is approximately like this
    Prop2_ADC_functional.png

    Evanh -- Let me ask one more question since you put up this diagram.
    will setting the different resistors in combination with the caps do a hardware filter of different values? I guessing because it is R-C type of filter.

    Looking at the inverter which receives input via the switches and capacitors in addition to negative feedback from the 300K resistor; then it would appear that because of the negative feedback from the flip flop and the other inverter, that if this was a purely analog signal the input to the inverter would act like a so-called virtual ground; just like an analog op-amp such as a 741, which is typically compensated with a capacitor that gives a 3db point of around 3 HERTZ, and yet such circuits achieve relatively flat frequency response easily out to hundreds of kilohertz and beyond because of the extremely high gain of the op-amp. Thus even if the capacitors had a value of infinity, there would be no effect on the frequency response, as long as the cascade of inverters that follows has enough gain (also approaching infinity) so that each infinitesimal voltage change that occurs with any input current is compensated by feedback pulses from the flip flop plus inverter. Of course real world inverters will have some hysteresis, and gain isn't infinite, so some upper limit on the size of the capacitors is desirable. Thus what the capacitors really do is help keep the input at (Vdd-Vss)/2 by not being overly sensitive to parasitic input to the inverters, as well as helping to enforce a "we would like a linear switched current" approach to the integration problem, so as to not have to contend with the RC time constants and Laplace transforms associated with voltage differences.
  • evanhevanh Posts: 8,975
    edited 2019-12-09 - 03:24:58
    CRST1 wrote: »
    will setting the different resistors in combination with the caps do a hardware filter of different values? I guessing because it is R-C type of filter.
    My skills on analogue aren't great. But my general knowledge here is that the principle of the sigma-delta design is the analogue cut-off frequency is way below the toggle frequency.

    Maybe just as importantly, Chip has said the real frontend is all done with current amplifiers. I believe the select resistors are there at the pin but they don't perform the balancing at the capacitors. The 300kR feedback resistor doesn't exist either, since that's also a current drive.
  • There definitely has to be an oscillation at the balance point. The information extracted is in the form of mark-space "pulse density" ratios. The balance toggling occurs as the ratio naturally unfolds in increments of the sys-clock, which itself is not just one set frequency.

  • evanh wrote: »
    The ADC frontend and bitstream modulator hardware in the prop2 is approximately like this
    Prop2_ADC_functional.png

    So the input range is 0 to 5V but with only 0 to 3.3V usable range due to protection diodes?

    What would be the optimum external circuit if I have a 0..5V source and want to read the full range? Is a simple divider enough, say 3.3kR + 6.8kR? The internal 450kR impedance would pull that a little bit off-center... I calculate 1.686V for 2.5V input to the divider and 3.36V for 5V input. The 450k:300k ratio means that I don't get a 0x3FFF reading for 14 bit range and 5V input but instead something around 0x2AAAA, right?

    Is additional anti-alias filtering required? Most other sigma-delta ADCs need an RC combination at the input.

  • evanhevanh Posts: 8,975
    edited 2019-12-16 - 16:04:14
    ManAtWork wrote: »
    So the input range is 0 to 5V but with only 0 to 3.3V usable range due to protection diodes?
    Yep, roughly. More precisely -0.3 to 3.6.

    What would be the optimum external circuit if I have a 0..5V source and want to read the full range? Is a simple divider enough, say 3.3kR + 6.8kR? The internal 450kR impedance would pull that a little bit off-center... I calculate 1.686V for 2.5V input to the divider and 3.36V for 5V input. The 450k:300k ratio means that I don't get a 0x3FFF reading for 14 bit range and 5V input but instead something around 0x2AAAA, right?
    Off the top of head, I'm not sure of the details. You're probably about right. EDIT: Those internal resistor values I plucked more from implied numbers than stated as being present. Chip indicated the diagram is a decent representation.

    Is additional anti-alias filtering required? Most other sigma-delta ADCs need an RC combination at the input.
    Nope, it's all there built in on every I/O pin.

  • Instrumentation drift of ADCs isn't well defined either. There was some discussions around using regular internal rail to rail calibration for nulling the drift.
  • Yet another question: The VIO/GND calibration feature, is that handled automatically or do I have to switch the input multiplexers manually and do 3 samples for every true input sample I want? I don't find much information in the data sheet about ADC modes.
  • No automatics, entirely for the software to handle.
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