ADC smartpin help needed
CRST1
Posts: 103
Ok all you guys out there smarter than me, that would probably be everyone.
I've gotten the counter and pwm pin modes working now with help.
Now I need some adc pins. Again confused about the descriptions.
The P2 document shows the wrpin instruction D operand as
Its showing %100011_00000000_ and there are 14 bits. The P's has only 13 bits.
I used the example to set up the pin but I am getting eratic values.
I've been looking at the chart for the P values but its not making sense. especially with the extra bit.
I tried grounding the pin and figured it should read 0 and hooked to 3.3 it should be maxed out.
I only reading the pin if the IN is high.
Can someone explain how the example sets up the pin for adc filtering?
Is the first 1 part of the %FFF part?
Meaning A and B, B and what does this mean
I've gotten the counter and pwm pin modes working now with help.
Now I need some adc pins. Again confused about the descriptions.
The P2 document shows the wrpin instruction D operand as
The Sinc3 filtering mode shows example:D/# = %AAAA_BBBB_FFF_PPPPPPPPPPPPP_TT_MMMMM_0
I understand the _00_11000_0,#adcpin part of it but the PPPPPPPPPPPPP part I am confused onTo begin SINC3 filtering:
WRPIN ##%100011_00000000_00_11000_0,#adcpin 'configure ADC+filter pin(s)
WXPIN #%10_0111,#adcpin 'SINC3 filtering at 128 clocks
DIRH #adcpin 'enable smart pin(s)
Its showing %100011_00000000_ and there are 14 bits. The P's has only 13 bits.
I used the example to set up the pin but I am getting eratic values.
I've been looking at the chart for the P values but its not making sense. especially with the extra bit.
I tried grounding the pin and figured it should read 0 and hooked to 3.3 it should be maxed out.
I only reading the pin if the IN is high.
Can someone explain how the example sets up the pin for adc filtering?
Is the first 1 part of the %FFF part?
Meaning A and B, B and what does this mean
%FFF: 'A' and 'B' input logic/filtering (after 'A' and 'B' input selectors)
000 = A, B (default)
001 = A AND B, B
010 = A OR B, B
011 = A XOR B, B
100 = A, B, both filtered using global filt0 settings
101 = A, B, both filtered using global filt1 settings
110 = A, B, both filtered using global filt2 settings
111 = A, B, both filtered using global filt3 settings
Comments
Have a read of my links if you haven't anyway, you should find them helpful - https://forums.parallax.com/discussion/comment/1483529/#Comment_1483529
You'll see I've divided the %P's up a little more than Chip does.
That %FFF filter is not for ADC. That's just a really basic three sample unanimous voting deglitcher for digital inputs.
Thanks
Is that the correct way with the ##%
The performance appears magical at first, then once you get to grips with the simplicity of implementation the maths behind it becomes mind boggling. If you ever get to grips with that then get yourself off to university.
Anyway, in the prop2, the accumulators and the first differentiator are in the smartpin. The remaining diffs are easy to perform in software.
The ADC frontend and bitstream modulator hardware in the prop2 is approximately like this
Further theoretical reading at http://www.ti.com/lit/an/slyt423a/slyt423a.pdf
Yep, that's correct. Yeah, sorry, spent too long writing the follow up post. You have to apply a second diff operation for SINC3 compared with SINC2. So it becomes
SUB x,diff1 ADD diff1,x SUB x,diff2 ADD diff2,xEDIT: Or is that what you're already doing?
asm dirl #17 wrpin ##%100011_0000000_00_11000_0, #17 wxpin #%10_0111, #17 dirh #17 endasmAnd thenrepeat if ina[17] == 1 asm rdpin x1, #17 sub x1, diff1 add diff1, x1 sub x1, diff1a add diff1a, x1 shr x1, #7 endasmNow I get -60765106 constant with voltage or ground on pin.
Edit: Was using the wrong var. The value is still erratic, doesn't chang when connected grnd or 3.3.
Value? You mean a long? I have x1 as a var in the main pub.
PUB Main | diff1, diff1a, x1
What do you mean huge numbers? What kind of values will it be?
Got me confused again. not hard to do!!
What kind of value would 0 volts give and 3.3 give?
I don't usally bother with the SHR at that stage so my PCM samples are somewhat larger. EDIT: And I have been known to experiment with higher than 512 clocks per decimation.
It comes in like this
Thank you for the help.
I tried the plain sampling mode and it works like I thought it should.
I guess I don't have a clue about what the filtering modes are about. I figured they would just be a more stable reading to filter out any noise in the signal. I guess my head can't absorb all the information.
Maybe in time someone will write a tutorial on how to use the smart pins like the counters on the P1.
Thanks, I think the sampling mode will work for now.
I don't really know much about the Spin language so someone else will have to give advise on how to make them persistent.
Yeh I haven't gotten into the persistent stuff about variables so far. Never needed to.
How about you writing the document about all these smart pin modes!!! haha!!
You're links do help some but I'm still dense until I see it work. So far I've got the counting, triangle PWM and this ADC figured far enough to start implementing it for this 4D systems display dashboard in my mustang.
Has to read tach, speed and fuel flow pulses, analog fuel level, oil press, temp and oxygen sensors and output PWM for rgb led lights.
Thanks again "evanh" and "cgracey" and all who responded.
Evanh -- Let me ask one more question since you put up this diagram.
will setting the different resistors in combination with the caps do a hardware filter of different values? I guessing because it is R-C type of filter.
Looking at the inverter which receives input via the switches and capacitors in addition to negative feedback from the 300K resistor; then it would appear that because of the negative feedback from the flip flop and the other inverter, that if this was a purely analog signal the input to the inverter would act like a so-called virtual ground; just like an analog op-amp such as a 741, which is typically compensated with a capacitor that gives a 3db point of around 3 HERTZ, and yet such circuits achieve relatively flat frequency response easily out to hundreds of kilohertz and beyond because of the extremely high gain of the op-amp. Thus even if the capacitors had a value of infinity, there would be no effect on the frequency response, as long as the cascade of inverters that follows has enough gain (also approaching infinity) so that each infinitesimal voltage change that occurs with any input current is compensated by feedback pulses from the flip flop plus inverter. Of course real world inverters will have some hysteresis, and gain isn't infinite, so some upper limit on the size of the capacitors is desirable. Thus what the capacitors really do is help keep the input at (Vdd-Vss)/2 by not being overly sensitive to parasitic input to the inverters, as well as helping to enforce a "we would like a linear switched current" approach to the integration problem, so as to not have to contend with the RC time constants and Laplace transforms associated with voltage differences.
Maybe just as importantly, Chip has said the real frontend is all done with current amplifiers. I believe the select resistors are there at the pin but they don't perform the balancing at the capacitors. The 300kR feedback resistor doesn't exist either, since that's also a current drive.
So the input range is 0 to 5V but with only 0 to 3.3V usable range due to protection diodes?
What would be the optimum external circuit if I have a 0..5V source and want to read the full range? Is a simple divider enough, say 3.3kR + 6.8kR? The internal 450kR impedance would pull that a little bit off-center... I calculate 1.686V for 2.5V input to the divider and 3.36V for 5V input. The 450k:300k ratio means that I don't get a 0x3FFF reading for 14 bit range and 5V input but instead something around 0x2AAAA, right?
Is additional anti-alias filtering required? Most other sigma-delta ADCs need an RC combination at the input.
Off the top of head, I'm not sure of the details. You're probably about right. EDIT: Those internal resistor values I plucked more from implied numbers than stated as being present. Chip indicated the diagram is a decent representation.
Nope, it's all there built in on every I/O pin.