Is there a detailed description of the smart pin modes ?

I admit I haven't been following the P2 development.

I have been playing with the P2 Eval board, and the one line description of each of the smart pin modes is really not very helpful.
Is there a more detailed document or post about each of the modes ?

I am trying to measure a low frequency (1KHz), but there is some jitter at the edges for about 500nSec.
The problem is that the counters on the P1 include this jitter in the count.
I need a way to ignore the signal for about 1uSec after each edge is detected.
Is there any way to do this on the P2 with the smart pins ?

Also from what I have read you need to use two smart pins to make a counter (one to count the system counter, and one to count the cycles). Is this true ?
What I would like to get is a count of the system clock cycles for 1000 cycles of the input signal. Is there a smart pin mode for that ?

Sorry for so many questions, but I'm really excited about using the P2.

Thanks,
Bean

Comments

  • evanhevanh Posts: 8,401
    edited 2019-11-20 - 00:00:43
    Parallax have just been updating the shop with all the good links - https://www.parallax.com/product/propeller-2
    There is links on the Eval Board shop page too. The detailed one on programming is the main Prop2 google doc.
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  • rjo__rjo__ Posts: 2,076
    edited 2019-11-20 - 03:28:56
    Bean,

    I am not a smart-pin guru... every time I want to use one, I ask... which you have done. And I would expect an answer shorty.

    Until then, there are probably six ways from Sunday to do it.
    When I think of jitter it is higher than normal fluctuations around a signal... since it is only happening at the entrance and exit of the signal and since you have a defined signal you are looking for, I would think that if you follow the first order differential in the signal it will peak at the edges. For a one off you wouldn't know ahead of time what kind of variations are typical for the signal and what is typical of jitter, but I would guess that after looking at it under expected conditions, which are probably measurable, you would have a pretty good idea. Plug those into your routine and you are good to go.

    The question is how to get power and frequency? Sounds like the Cordic to me:) I have seen it used like this... but haven't actually done it myself. AND I also can't remember where the many examples are. Have to be careful with the examples on the smart pins... that stuff has changed in the final silicon. The Cordic stuff? I think that has been stable for a while, but I really don't know.

    Regards,

    Rich
  • cgraceycgracey Posts: 11,954
    edited 2019-11-20 - 04:17:41
    Bean, you'll want to use the "reciprocal counter" that jmg campaigned for. I don't know the mode number, but it's in the Google doc. Do you have that up? After the one-line descriptions of all modes, they are each elaborated on, further down in the document.

    This thread has links to the Google doc/sheet files:

    http://forums.parallax.com/discussion/170380/new-p2-silicon/p1
  • evanhevanh Posts: 8,401
    edited 2019-12-02 - 01:27:12
    Bean wrote: »
    What I would like to get is a count of the system clock cycles for 1000 cycles of the input signal. Is there a smart pin mode for that ?
    Yep, smartpin mode %10011 or %10010 singularly will provide exactly that no problem, but the jitter will still be present. The way I'd deal with the jitter is filter multiple readings/samples to produce a smoothed measurement.

    Here's a summary of smartpin counter modes. For making it easier to choose the right mode without reading every detail of every mode first.
    	SPM_CNT_QUAD	= %01011_0		' count: A-B quadrature encoder
    	SPM_CNT_UP_ENA	= %01100_0		' count: A clock up, B enable
    	SPM_CNT_DIR	= %01101_0		' count: A clock, B direction
    	SPM_CNT_UP	= %01110_0		' count: (Y=%0) A clock up
    	SPM_CNT_UP_DN	= %01110_0		' count: (Y=%1) A clock up, B clock down
    	SPM_ACC_UP	= %01111_0		' accumulate: (Y=%0) A up
    	SPM_ACC_UP_DN	= %01111_0		' accumulate: (Y=%1) A up, B down
    	SPM_TIM_STEP	= %10000_0		' interval: of most recent step duration
    	SPM_TIM_PULSE	= %10001_0		' interval: of most recent pulse duration
    	SPM_TIM_MANY	= %10010_0		' interval: (Y=%0xx) of X number of accum/pulses/steps
    	SPM_TIMEOUT	= %10010_0		' interval: (Y=%1xx) since most recent high/rise/edge, with X compare
    	SPM_TIM_PULS	= %10011_0		' interval: of X number of A-B pulses/steps
    	SPM_ACC_PULS	= %10100_0		' accumulate: pulses/steps, of X number of A-B pulses/steps
    	SPM_TIM_OVER	= %10101_0		' interval: of A-B pulses/steps, for at least X duration
    	SPM_ACC_OVER	= %10110_0		' accumulate: A-B pulses/steps, for at least X duration
    	SPM_CNT_OVER	= %10111_0		' count: A-B pulses/steps, for at least X duration
    

    EDIT: 2-12-2019 Add commented config detail to the three pair of counter modes that have duplicate mode numbers
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  • jmgjmg Posts: 14,152
    edited 2019-11-20 - 07:03:53
    Bean wrote: »
    Also from what I have read you need to use two smart pins to make a counter (one to count the system counter, and one to count the cycles). Is this true ?

    For widest dynamic range, yes, the Reciprocal Counter (which you know well), is the ideal.
    You may also want a TCXO or VCTCXO etc timebase ....

    Bean wrote: »
    What I would like to get is a count of the system clock cycles for 1000 cycles of the input signal. Is there a smart pin mode for that ?
    I think yes, if you know the fixed cycles you want to time over, you can use a simpler design and a single smart pin, I think this mode, with X[31:0] = 1000
    SPM_TIM_MANY	= %10010_0	' interval: of X number of accum/pulses/steps
    
    Bean wrote: »
    I am trying to measure a low frequency (1KHz), but there is some jitter at the edges for about 500nSec.
    The problem is that the counters on the P1 include this jitter in the count.
    I need a way to ignore the signal for about 1uSec after each edge is detected.
    Is there any way to do this on the P2 with the smart pins ?

    The issue here is unclear.
    If you simply delay on a jittery edge, you still have jitter ?
    If you meant the edge can have noise inside that 500ns, or multiple possible edges, then 'ignore the signal' is a blanking or filter operation.

    Yes, P2 does have noise filtering, as in the DOCs
    2/3/5/8-bit-unanimous input filtering with selectable sample rate

    and see
    Configuring the Digital Filters for Smart Pins

    A Over-1000-cycles Timer interval capture (nominally 1 second update at 1kHz) with a 1us edge pin filter would be a great P2 example :)

  • That simple hardware filter won't remove true jitter but it will remove spurious unwanted glitches ... including gaps in the signal. Maybe Bean is after that ... or not, dunno.

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  • Thanks for all the good information.

    The signal is a triangle wave that is "squared-up" with an inverter gate.
    Right at the transition voltage the output of the gate will toggle a couple times.
    I can't use a schmitt gate because there is not enough voltage swing to trigger it.

    I might be able to apply some positive feedback, but I can't try that at the moment.

    Bean
  • dMajodMajo Posts: 779
    edited 2019-11-20 - 17:07:41
    @Bean if you plan to use eg a 3.3V cmos inverter gate this means that your input uncertainty region, which the signal have to swing/cross, goes from 0.8V to 2V.

    You can use a schmitt-trigger inverter like this and supply it with lower voltage eg 2.4Vcc instead of 3.3V.
    This will give you negative threshold of 0.69/1.04V and positive threshold of 1.37/1.77V on input side while still producing acceptable cmos levels, readable by 3.3v supplied logic, on output side.

    Edit: Since there is practically no current load on the P2 input, you can probably even supply the single gate through a P2-DAC output and thus adjust the power supply voltage on the fly. The gate's static power consumption is less than a uA.
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  • I want to measure multiple inputs at the same time.
    I also do not want to miss ANY cycles (no dead-time).
    The frequencies are low (about 10KHz or less), so I could process the data in code.

    What I think would work for me would be if the smart pin had a constant counter running at the system clock, and it would latch that counter value when the input pin goes low-to-high.
    Bonus would be if would only latch one time until being re-triggered, to deal with the jitter, but that's another problem.

    In the main code I could repeatedly read the latched values and if they changed, I could calculate the period of each cycle of each input.

    Looking at the different smart pin modes, nothing stands out to me as being able to do this.
    Am I missing anything ? If not I'll keep experimenting to see if there is way to do it.

    Bean
  • jmgjmg Posts: 14,152
    Bean wrote: »
    I want to measure multiple inputs at the same time.
    I also do not want to miss ANY cycles (no dead-time).
    The frequencies are low (about 10KHz or less), so I could process the data in code.

    What I think would work for me would be if the smart pin had a constant counter running at the system clock, and it would latch that counter value when the input pin goes low-to-high.
    Bonus would be if would only latch one time until being re-triggered, to deal with the jitter, but that's another problem.

    In the main code I could repeatedly read the latched values and if they changed, I could calculate the period of each cycle of each input.

    Looking at the different smart pin modes, nothing stands out to me as being able to do this.
    Am I missing anything ? If not I'll keep experimenting to see if there is way to do it.
    The mode I mentioned above looks the best, it saves pins if you know how many cycles to expect/time.
    You could run ~60 of those in P2.
    Bean wrote: »
    I also do not want to miss ANY cycles (no dead-time).

    Chip's docs are sparse, but I think all Time interval capture modes include this feature, mentioned in another mode :
    "If a non-zero value is used for the period, events will be counted for that many clock cycles and then the result will be placed in Z, while the accumulator will be set to the 0/1/-1 value that would have otherwise been added into it, beginning a new measurement. This way, all events get counted across measurements."


    ie a Capture and Clear includes HW compensation for a possible edge on the same sysclk as capture/clear, which means there is no dead times, and multiple measurements can be summed for very high precisions.
    A common use would be a Frequency counter that reports to ppm rapidly (readings per second), and also reports to ppb over 10's of seconds with a simple sum of those no-dead-time captures.
    Bean wrote: »
    The signal is a triangle wave that is "squared-up" with an inverter gate.
    Right at the transition voltage the output of the gate will toggle a couple times.
    I can't use a schmitt gate because there is not enough voltage swing to trigger it.
    Multiple edges effects should be possible to pin-filter. You would need to experiment with that.
    I'd think the lower filter-clock sampling rates would have their own quanta effects, but if you have 500ns of fur, that's already uncertainty
    Some gates have a natural oscillation frequency, so the edge fur is less random, and more a burst. If you check the MHz of that, that might guide the filter settings.
    If you really want to react to first-edge, then an external monostable would be needed.

    I'd guess that a filter mode with max 8-flops and a 125ns clock tap, should give 1us of fur-width rejection, and 125ns of quantize, but a high-MHz fur could degrade that quanta for simple sampling reasons. eg imagine if the 125ns pickets align with low-cycles on one burst, and then align with high-cycles on the next.
    One edge will be 1us left and one will be 1us right, If the edge fur is 250~500ns, you will get more expected filter operation. Part selection may help there ?


    What is the lowest frequency/lowest amplitude and thus the widest 'edge fur' band you need to tolerate.
    There are comparator parts with low hysteresis - what swing do you have ? & what gate do you use currently ?

  • Bean,
    It sounds a little like the measurement you're after is the high to low ratio of the triangle?

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  • evanhevanh Posts: 8,401
    edited 2019-12-02 - 01:45:05
    Bean,
    Did you get this sorted in the end?

    It wasn't clear to me what the primary signal component was intended to be. Initially it seemed to be the time over which a series of triangle pulses occurred. But then it seemed more like the average high/low ratio of those pulses is desired.

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  • Evan, Right now I am using the squared up triangle wave with the smartpin modes, but that doesn't address the edge jitter.
    But I will work on that after I get more comfortable with the P2.

    Bean
  • Hmm, that didn't really answer.
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  • AJLAJL Posts: 218
    edited 2019-12-02 - 03:43:18
    evanh wrote: »
    Hmm, that didn't really answer.

    Agreed.

    I'm thinking that if @Bean is looking to trigger an action when the triangle wave crosses a particular threshold level, the P2 could do it without the inverter if it stays inside the 3.3V limit.

    Simply use the ADC sample/filter/capture, internally clocked mode on a pin to measure the signal directly (with RDPIN) and have the code decide the action that way.
    The 64 bit system counter should allow simple measurement of the time elapsed between events; even at 300 MHz the rollover period is just short of 2000 years since the last reset.

    The P2 way won't always be a small adjustment to the P1 way, but may benefit from a complete re-think of the problem.
  • AJL, I remember something about the P2 being able to set the threshold voltage. Is that what you are talking about ?
    If not, is there a way to set the threshold voltage ? For example to be 1.0V ? If so how is that setup ?

    Thanks,
    Bean
  • evanhevanh Posts: 8,401
    edited 2019-12-02 - 13:54:01
    There is an input comparator in each pin, the reference level can be internally set using the DAC in that pin. I've called it the COMP_DAC mode. I figure in steps of 12.94 mVolts, but it is dependant on the stability of the VIO supply volts.

    However, if you'd tell us the type of signal you're trying measure then we can probably recommended a solution that doesn't involve the noisy threshold you're dealing with. Further reading - https://forums.parallax.com/discussion/comment/1483529/#Comment_1483529

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  • jmgjmg Posts: 14,152
    evanh wrote: »
    There is an input comparator in each pin, the reference level can be internally set using the DAC in that pin. I've called it the COMP_DAC mode. I figure in steps of 12.94 mVolts, but it is dependant on the stability of the VIO supply volts.
    I don't see mention of hysteresis levels, and offset errors on the comparator ?

    The Digital Filters for Smart Pins will give some edge rejection, but they will have their own sampling quanta.
    If the application wants edge-fur rejection, and best first-edge time resolve, I think a form of monostable is needed.
    Not sure if one can be crafted from smart pins ?

    I think pin hysteresis can be synthesized using 'PinA driven by 1k5R from IN' mode, and some series drive R ?
    Maybe that is 'monostable enough' - an RC filter needs to reduce the fur effects, to less than Hyst change ?
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