P2 Eval Board Owners, I need your help!

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  • jmgjmg Posts: 13,937
    cgracey wrote: »
    Good news!

    The big boss at ON Semi gave word to the test engineer to start working with me on the current-limiting procedure for the start of the test. The engineer and I talked and we've got a plan of attack:

    1) Hold TESn, RESn, and P[63:0] at GND.
    2) Set VDD as a 1mA source, clamped to 1.8V. (typical leakage is ~100uA)
    3) Set VIO as a 100uA source, clamped to 3.3V. (typical leakage is ~10uA)
    4) Allow 3ms for any attached bypass caps to charge.
    5) Verify that VDD and VIO currents are not clamped at limits, else fail.
    6) Set sufficient/safe VDD and VIO limits.
    7) Proceed to regular test suite.

    This will detect shorted dies right off the bat and preserve delicate test fixtures. We can get the known-good die sorted for Amkor packaging, then.

    Great :)
    1mA and 100uA sound a bit light, as they are damage-avoidance, maybe 5mA/500uA can speed the tests ?
    I think 5) means verify VDD & VIO have reached clamp voltage limits, else fail..

    cgracey wrote: »
    Good news!
    He said these shorted die were located near the edge of the wafer, by the way, where yield typically drops off.
    I had wondered if die location affected things, would be interesting to see a final fail-scatter graph of die locations when they are all done.

  • cgraceycgracey Posts: 11,711
    edited 2019-08-20 - 04:09:38
    jmg wrote: »
    ...
    1mA and 100uA sound a bit light, as they are damage-avoidance, maybe 5mA/500uA can speed the tests ?
    I think 5) means verify VDD & VIO have reached clamp voltage limits, else fail..

    I agree about the higher current.

    Yes, the way I stated 5) sounds odd, but means the same thing you wrote. It is how the test engineer said he will have to configure the tester.
  • This is great news Chip! Glad to see forward progress!
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  • cgracey wrote: »
    The engineer and I talked and we've got a plan of attack

    That's the important bit right there.
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  • cgraceycgracey Posts: 11,711
    edited 2019-08-20 - 04:35:28
    The big boss at ON Semi doesn't say much, but I think he makes sensible decisions. Certainly, he's looking out for ON's bottom line.

    He's the guy who was originally involved in the P2 project quote and later identified the I/O pin glitch on the 1st silicon as a race condition. He was onto other things for a while, but got re-involved when it was taking a long time to get the 2nd silicon taped out. He really didn't like hearing that we had added 64 flops on the input pins to get around potential metastability problems per Wendy's recommendation, calling it "feature creep". We realized it was probably best to stay silent about those other 5,500 flops we just added for new features. He didn"t know about the clock-gating, either. He had been quite out of the loop for a while. He barely permitted me to change the PLL filter on the 2nd silicon, and I was afraid to push further for lightening up the ADC integrator cap. Everything worked out, though.
  • jmgjmg Posts: 13,937
    cgracey wrote: »
    The big boss at ON Semi doesn't say much, but I think he makes sensible decisions. Certainly, he's looking out for ON's bottom line.

    He's the guy who was originally involved in the P2 project quote and later identified the I/O pin glitch on the 1st silicon as a race condition. He was onto other things for a while, but got re-involved when it was taking a long time to get the 2nd silicon taped out. He really didn't like hearing that we had added 64 flops on the input pins to get around potential metastability problems per Wendy's recommendation, calling it "feature creep". We realized it was probably best to stay silent about those other 5,500 flops we just added for new features. He didn"t know about the clock-gating, either. He had been quite out of the loop for a while. He barely permitted me to change the PLL filter on the 2nd silicon, and I was afraid to push further for lightening up the ADC integrator cap. Everything worked out, though.

    Sounds like he has ample experience :)
    Is he involved enough to comment on your MHz bench tests, and what they might mean for final data sheet specification points ? He may have a feel for typical to spec-minimums margins in their process.
  • cgraceycgracey Posts: 11,711
    edited 2019-08-20 - 05:47:56
    jmg wrote: »
    cgracey wrote: »
    The big boss at ON Semi doesn't say much, but I think he makes sensible decisions. Certainly, he's looking out for ON's bottom line.

    He's the guy who was originally involved in the P2 project quote and later identified the I/O pin glitch on the 1st silicon as a race condition. He was onto other things for a while, but got re-involved when it was taking a long time to get the 2nd silicon taped out. He really didn't like hearing that we had added 64 flops on the input pins to get around potential metastability problems per Wendy's recommendation, calling it "feature creep". We realized it was probably best to stay silent about those other 5,500 flops we just added for new features. He didn"t know about the clock-gating, either. He had been quite out of the loop for a while. He barely permitted me to change the PLL filter on the 2nd silicon, and I was afraid to push further for lightening up the ADC integrator cap. Everything worked out, though.

    Sounds like he has ample experience :)
    Is he involved enough to comment on your MHz bench tests, and what they might mean for final data sheet specification points ? He may have a feel for typical to spec-minimums margins in their process.

    He may not have much to say about overclocking, as ON is very conservative about making sure they deliver on the specification. He might even get concerned about hearing of end customers' expectations being upped.
  • No surprise there. The design is for 180 MHz, that's the end of the MHz discussion for On Semi.
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  • evanh wrote: »
    No surprise there. The design is for 180 MHz, that's the end of the MHz discussion for On Semi.

    We actually had to close timing at 175MHz on this last silicon. We would have been climbing the wall, trying to get 180MHz. This silicon is faster, though, because it doesn't self-heat nearly as much as the first silicon did.
  • We realized it was probably best to stay silent about those other 5,500 flops we just added for new features.

    I have to snicker. Well played. Yes, that was probably wise. This guy has to be ultra conservative. It's a rough game, big wins, big losses.

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  • potatohead wrote: »
    We realized it was probably best to stay silent about those other 5,500 flops we just added for new features.

    I have to snicker. Well played. Yes, that was probably wise. This guy has to be ultra conservative. It's a rough game, big wins, big losses.

    Yeah, I didn't realize that he was unaware that the logic had grown by 15%, or that he would have had a problem with that. He thought we were just fixing the sign-extension problem and the pin glitching. It took them months to get back on the job after we expressed the need for a respin, so I had been enhancing the design the whole time.
  • I wonder whether you're the only customer who's run into that verilog sign extension issue. I suspect not. Tough lesson, it'll probably catch others unawares too


  • Tubular wrote: »
    I wonder whether you're the only customer who's run into that verilog sign extension issue. I suspect not. Tough lesson, it'll probably catch others unawares too


    If you run simulations from the synthesized logic, it will show up. In our case, the simulations were limited to booting and a few downloaded programs, none of which exercised the buggy circuits. It's one of those cases of not knowing about what you don't know.
  • Nice, Chip. You should keep the ON Semi big boss in the dark, hehe.

    Anyway, I'm glad to read that part of the second wafer can be used too.

    Kind regards, Samuel Lourenço
  • cgraceycgracey Posts: 11,711
    edited 2019-08-20 - 13:54:36
    samuell wrote: »
    Nice, Chip. You should keep the ON Semi big boss in the dark, hehe.

    Anyway, I'm glad to read that part of the second wafer can be used too.

    Kind regards, Samuel Lourenço

    I got surprised and scared when he was reacting over 64 flops, so I didn't want to say anything. His concern was that it was taking too long for their engineers to wrap up the layout, and it was running over-budget. He definitely had the idea that engineers will just keep adding things onto a design, and he needed to put his foot down. I figured, for that $82k respin charge, it wasn't going to be an issue. I'm sure he operates under continuous pressure to control costs.
  • edited 2019-08-20 - 17:52:57
    cgracey wrote: »
    I got surprised and scared when he was reacting over 64 flops, so I didn't want to say anything.

    Hope he doesn't visit this forum. :crazy:
    Infantryman's Axiom; Always cheat, always win.
  • cgracey wrote: »
    I got surprised and scared when he was reacting over 64 flops, so I didn't want to say anything.

    Hope he doesn't visit this forum. :crazy:

    He'll know this someday - after things have proven successful, hopefully.
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