P2 opcode mask/match questions

pullmollpullmoll Posts: 799
edited 2019-08-11 - 17:09:57 in Propeller 2
Since I have no P2 yet I started writing an emulator. I want to exercise some code on my box.

I used P2 instruction set.csv to extract the opcode bit masks and match values in order to decode the instruction.
However, I have duplicate entries for two groups of instructions now.

With mask 0x0fe001ff (binary 0000_1111111_000_000000000_111111111) I get this
DIRL, DIRH, DIRC, DIRNC, DIRZ, DIRNZ, DIRRND, DIRNOT
EEEE 1101011 CZL DDDDDDDDD 001000xxx
and also
TESTP WC/WZ, TESTPN WC/WZ, TESTP ANDC/ANDZ, TESTPN ANDC/ANDZ, TESTP ORC/ORZ, TESPN ORC/ORZ, TESTP XORC/XORZ, TESTPN XORC/XORZ
EEEE 1101011 CZL DDDDDDDDD 001000xxx

The other group of clashing is with mask 0x0fe00000 (binary 0000_1111111_000_000000000_000000000)
BITL, BITH, BITC, BITNC, BITZ, BITNZ, BITRND, BITNOT
EEEE 0100xxx CZI DDDDDDDDD SSSSSSSSS
and also
TESTB WC/WZ, TESTBN WC/WZ, TESTB ANDC/ANDZ, TESTBN ANDC/ANDZ, TESTB ORC/ORZ, TESTBN ORC/ORZ, TESTB XORC/XORZ, TESTBN XORC/XORZ
EEEE 0100xxx CZI DDDDDDDDD SSSSSSSSS

Am I missing something, or is this a bug in the table?

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Comments

  • Yes, there are a lot of instructions that make use of either the D operand, the S operand, and/or the WC, WZ, I bits. There is a list of instructions and their bit fields in the P2 tricks and traps thread. There are twi tables i published there, one is just the P2 equivalents for P1 instructions.
    BTW there is no NR (no write) bit and the conditional instruction bits “0000” for never is now used for always plus a return instruction on an existing instruction with no time penalty. There is an 8 level stack.
    My Prop boards: P8XBlade2, RamBlade, CpuBlade, TriBlade
    Prop OS (also see Sphinx, PropDos, PropCmd, Spinix)
    Website: www.clusos.com
    Prop Tools (Index) , Emulators (Index) , ZiCog (Z80)
  • The BITx instructions will never us WC or WZ, so when they are set they decode to a different set of instructions that require WC and/or WZ to be set. It’s all very clever, but much harder to decode.
    My Prop boards: P8XBlade2, RamBlade, CpuBlade, TriBlade
    Prop OS (also see Sphinx, PropDos, PropCmd, Spinix)
    Website: www.clusos.com
    Prop Tools (Index) , Emulators (Index) , ZiCog (Z80)
  • jmgjmg Posts: 13,932
    pullmoll wrote: »
    Since I have no P2 yet I started writing an emulator.
    I think there are P2 Software Simulators / Emulators already - someone may have links/status on ES revision number support etc ?
    Not sure if any of the P2 debug efforts include a software simulator mode ?
    Someone also experimented with a Verilog derived simulator for the P1V.

    eg https://forums.parallax.com/discussion/161755/p2-simulator

  • msrobotsmsrobots Posts: 2,913
    edited 2019-08-11 - 22:09:12
    pullmoll wrote: »
    Since I have no P2 yet I started writing an emulator...

    Gosh Guys, I was rooting for this, My favorite other German Member is back. Now things will get funny if @pullmoll starts to bite into something I can start to learn stuff from him again!

    Just wonderful.

    Now @TonyB_, @Cluso99 and me have a real challenge to get a Z-80 bytecode interpreter done, before he does... :smile:

    Even without actual P2.

    Enjoy!

    Mike
    I am just another Code Monkey.
    A determined coder can write COBOL programs in any language. -- Author unknown.
    Press any key to continue, any other key to quit

    The key words "MUST", "MUST NOT", "REQUIRED", "SHALL", "SHALL NOT", "SHOULD", "SHOULD NOT", "RECOMMENDED", "MAY", and "OPTIONAL" in this post are to be interpreted as described in RFC 2119.
  • @msrobots After realizing how useless one's existence in this complicated instance of reality actually is, i.e. if you dared to SUBX or even SUBSX all your bad attitudes from $SELF, I thought I could just as well do something useful for a try.

    @Cluso99 I think I can see where my fault is, or where there's something peculiar in the docs: for the BITL etc. group WCZ is optional, but not one of WC or WZ alone, while for TESTP/TESTB either one of the WC or WZ bits are required, but not both at the same time. So it's all about creating the correct mask: if (C xor Z == 0) then BITL else TESTP/TESTB. Tricky!
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  • ersmithersmith Posts: 3,409
    edited 2019-08-11 - 23:53:58
    @Dave Hein's spinsim emulator supports both P1 and P2. It's available at:

    https://github.com/parallaxinc/spinsim

    (I should note that "spinsim" is not an accurate name any more, it emulates raw processor instructions... although I think the bytecode emulator is still in there somewhere)
  • @pullmoll,

    you will enjoy the P2, it's tricky because it's Chips way. But very efficient, sometimes 30 lines of code shrink to two or three using smart pins. Have fun!

    Mike
    I am just another Code Monkey.
    A determined coder can write COBOL programs in any language. -- Author unknown.
    Press any key to continue, any other key to quit

    The key words "MUST", "MUST NOT", "REQUIRED", "SHALL", "SHALL NOT", "SHOULD", "SHOULD NOT", "RECOMMENDED", "MAY", and "OPTIONAL" in this post are to be interpreted as described in RFC 2119.
  • Cluso99Cluso99 Posts: 15,410
    edited 2019-08-12 - 05:15:14
    @pullmoll,
    You will appreciate the xbyte and skip/skip instructions for emulators, although from what I can see, it’s of limited use for z80 emulation.
    You will also like that we can run straight out of hub (hubexec) at full speed, without the lmm interpreter. There is just the wait for the hub cycle to come around every time the hub address jumps. So if you had 100 instructions without jumps, it would take just the initial hub latency to get going (~4-11 clocks) then every instruction will be 2 clocks with the few exceptions and hub read/writes. Nifty eh!

    BTW I have your qz80 converted for P2. About to try it out :smiley:
    Then I need to get CPM running.
    My Prop boards: P8XBlade2, RamBlade, CpuBlade, TriBlade
    Prop OS (also see Sphinx, PropDos, PropCmd, Spinix)
    Website: www.clusos.com
    Prop Tools (Index) , Emulators (Index) , ZiCog (Z80)
  • pullmollpullmoll Posts: 799
    edited 2019-08-12 - 12:03:23
    I already saw the xbyte Z80 emulator code and was impressed. I also read about skip and especially skipf in the docs, which can be utilized to dramatically reduce the COG space required to emulate orthogonal instruction sets like the 8080/8085 and Z80 are.

    I also saw your qz80 changes and am sure that once it works it can be optimized (read: shrunk) for the P2 quite a bit.
    I can hardly wait to get my hands on a P2 board :wink:

    I've been working on a Qt5 project to emulate the P2 for about 15 hours now: defining enumerations for the flags and opcodes, the structure of the 32 instruction bits as bit fields, C++ templates to nicely handle required type casting etc. and several hundred op_xxx() functions for handling of each instruction. The latter were generated with comments taken from the CSV.
    It's fun to flesh out the code and wrap my mind around how to efficiently do in C++ what the P2 does... well, enough babbling already :blush:
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  • I cannot wait for you to get a P2 too. What you did on P1 in such a short time was simply amazing!
    It’s probably not worth the trouble of finding an FPGA Nano-A9 at this late stage, or a a P2-EVAL lying idle.
    My Prop boards: P8XBlade2, RamBlade, CpuBlade, TriBlade
    Prop OS (also see Sphinx, PropDos, PropCmd, Spinix)
    Website: www.clusos.com
    Prop Tools (Index) , Emulators (Index) , ZiCog (Z80)
  • Formerly known as TonyB
  • TonyB_TonyB_ Posts: 1,294
    edited 2019-08-12 - 14:22:16
    deleted
    Formerly known as TonyB
  • pullmollpullmoll Posts: 799
    edited 2019-08-18 - 00:22:37
    FWIW: Here's my Propeller2 emulator repository on github.com.
    21 00 00 11 01 00 01 ff ff af 12 ed b0
  • pullmoll wrote: »
    FWIW: Here's my Propeller2 emulator repository on github.com.

    I think the spreadsheet at http://forums.parallax.com/discussion/162298/prop2-fpga-files-updated-2-june-2018-final-version-32i/p1 is not up-to-date. I've attached the final version of the instruction set. New SETSCP & GETSCP added and RDLUT & WRLUT modified, the latter are the important ones for an emulator.
    Formerly known as TonyB
  • Thank you @TonyB_ I'll use that for further reference.
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  • I may be ignorant but I haven't found the P2 ROM code, i.e. what's executed when the P2 is powered up. It should be contained somewhere in the archives, yet I failed to track it down.
    Does someone have a pointer to a ZIP or the file(s)?
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  • rosco_pcrosco_pc Posts: 338
    edited 2019-08-15 - 19:44:19
    Stockholm, Sweden
    I am only an egg -- Stranger in a Strange land, Robert A. Heinlein
  • The ROM code is actually copied to hub RAM $FC000 from a serial rom inside the chip on power up, then a JMP $FC000 executes. So effectively the boot starts at the beginning of the ROM listing.
    v32i is the ES version and v32j is the respin (Aug 2019).
    My Prop boards: P8XBlade2, RamBlade, CpuBlade, TriBlade
    Prop OS (also see Sphinx, PropDos, PropCmd, Spinix)
    Website: www.clusos.com
    Prop Tools (Index) , Emulators (Index) , ZiCog (Z80)
  • pullmollpullmoll Posts: 799
    edited 2019-08-16 - 00:33:43
    Ok, these references are to *.spin2 files which suggests I have to build the binary images using p2asm or PNut.exe on Windows. I'll try and see if I can add some binary file into the project to bootstrap the emulation, or test the disassembler.
    21 00 00 11 01 00 01 ff ff af 12 ed b0
  • pullmoll wrote: »
    Ok, these references are to *.spin2 files which suggests I have to build the binary images using p2asm or PNut.exe on Windows.
    fastspin can also build the ROM images. Both p2asm and fastspin work on Linux and MacOS, I think.
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