Looking for FPGA board

Comments

• jmg Posts: 15,144

  2018-06-06 22:26

  thej wrote: »

  I'm looking for an FPGA board for P2 development but I'm having problems finding them for purchase (and fitting my budget).
  
  The Prop123 is out of my budget (dang!) and the DE0-nano does not have CORDIC.
  
  I need a board that can support at least:
  -one Cog
  -64K RAM & the 16K ROM
  -8 Smart pins
  -CORDIC
  Everything else is a bonus :-)
  
  I'm looking at Terasic's page and the DE10-nano (110k LEs) and the DE0-CV (49K LEs) look good and are affordable.
  But are they supported !?! Is there an image for them?
  
  Alternatively, the BeMicro CV might work (25k LEs) but I can't find it anywhere to buy.
  Can it fit the CORDIC unit?
  
  
  DE10-nano
  http://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=165&No=1046
  
  DE0-CV
  http://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=165&No=921&PartNo=1
  
  Jason

  
  Boards listed are in this thread
  https://forums.parallax.com/discussion/162298/prop2-fpga-files-updated-2-june-2018-final-version-32i/p1
  Looks like DE2-115 is the smallest supported one that can fit cordic. (which is the toughest requirement, once you have cordic, everything else is ample..)
  

  			  smart
  	           cogs	  pins	RAM	Freq	CORDIC	Filename
  	         +-----------------------------------------------------------------------------------------
  Prop123-A9       |  16	   7	 1024k	80MHz	Yes	Prop123_A9_Prop2_16cogs_v32i.rbf	- not ready
  Prop123-A9       |  8	  64	  512k	80MHz	Yes	Prop123_A9_Prop2_8cogs_v32i.rbf **	- READY
  BeMicro-A9       |  16	   7	 1024k	80MHz	Yes	BeMicro_A9_Prop2_16cogs_v32i.jic *	- not ready
  BeMicro-A9       |  8	  64	  512k	80MHz	Yes	BeMicro_A9_Prop2_8cogs_v32i.jic */**	- READY
  Prop123-A7       |  4	  38	  512k	80MHz	Yes	Prop123_A7_Prop2_v32i.rbf		- READY
  DE2-115          |  4	  20	  256k	80MHz	Yes	DE2_115_Prop2_v32i.pof *		- READY
  BeMicro-A2       |  1	   7	  128k	80MHz	No	BeMicro_A2_Prop2_v32i.jic *		- READY
  DE0-Nano         |  1	   8	   32k	80MHz	No	DE0_Nano_Prop2_v32i.jic			- READY
  DE0-Nano Bare    |  1	   8	   32k	80MHz	No	DE0_Nano_Bare_Prop2_v32i.jic		- READY
  
  *  These images always map SD card pins {CSn,CLK,DO,DI} into P[61:58].
  ** These images represent the logic and memory that will be built in silicon.
  

  
  DE2-115 seems to ue
  EP4CE115F23I7N Cyclone® IV E Active 7155 LAB 114480 LE 3981312 RAMb
  
  DE10-NANO
  5CSEBA6U23I7N 47 - Immediate $246.42000 Cyclone® V SE Dual ARM® Cortex®-A9 MPCore™ with CoreSight™ 64KB
  DMA, POR, WDT CAN, EBI/EMI, Ethernet, I²C, MMC/SD/SDIO, SPI, UART/USART, USB OTG 800MHz FPGA - 110K Logic Elements
  
  P0496 Terasic Inc. DE10-NANO CYCLONE V SE SOC KIT 1,252 - Immediate $130.00000
  
  Notice the DE10-Nano price is well under the chip price !
  
  DE0-CV is more $ and only 49k LE, so the DE10-Nano looks viable, but right now there is no compiled image for that.
• thej Posts: 232

  2018-06-06 22:53

  Thanks JMG ! This is an awesome overview!
  
  @cgracey Any chance of a DE10-Nano compile??
  
  Jason
• Tubular Posts: 4,621

  2018-06-06 22:58

  Wonder how many LE's the Cordic is
• jmg Posts: 15,144

  2018-06-06 23:03

  Tubular wrote: »

  Wonder how many LE's the Cordic is

  
  Interesting question, but nothing on the current list has spare room to meet the other requirements, and add a cordic.
• cgracey Posts: 14,133

  2018-06-07 01:48

  Tubular wrote: »

  Wonder how many LE's the Cordic is

  
  20k LE's or about 8k ALM'S.
• KMyers Posts: 433

  2018-06-07 22:50

  I just got a DE NANO 10, been reading and playing but not with Prop2. Would also love to see a small build for it also.
  
  Ken
• thej Posts: 232

  2018-06-07 23:00

  How many other people would do testing on the P2 if there was a DE10-nano image?
  It's inexpensive and can accommodate a decent portion of the P2.
  
  Jason
• KMyers Posts: 433

  2018-06-08 18:38

  I would love to help.
• wmosscrop Posts: 406

  2018-06-11 13:21

  I would like to help also.
• K2 Posts: 691

  2018-06-12 03:38 edited 2018-06-12 03:39

  With CORDIC installed, is it reasonable to expect the DE10-nano could still host four COGs?
• jmg Posts: 15,144

  2018-06-12 03:49

  K2 wrote: »

  With CORDIC installed, is it reasonable to expect the DE10-nano could still host four COGs?

  
  It's 'reasonable', but would only be known if Chip decides to add a build for the DE10-NANO 5CSEBA6U23I7N
• ozpropdev Posts: 2,791

  2018-06-12 04:34

  FYI Here's the stats for a standard P1V build for the DE10_Nano for reference.
  PortA only with 32K Hub and 8 cogs.
  

  Flow Status	Successful - Tue Jun 12 14:26:44 2018
  Quartus Prime Version	17.0.0 Build 595 04/25/2017 SJ Lite Edition
  Revision Name	top
  Top-level Entity Name	top
  Family	Cyclone V
  Device	5CSEBA6U23I7
  Timing Models	Final
  Logic utilization (in ALMs)	7,496 / 41,910 ( 18 % )
  Total registers	5937
  Total pins	42 / 314 ( 13 % )
  Total virtual pins	0
  Total block memory bits	655,360 / 5,662,720 ( 12 % )
  Total DSP Blocks	0 / 112 ( 0 % )
  Total HSSI RX PCSs	0
  Total HSSI PMA RX Deserializers	0
  Total HSSI TX PCSs	0
  Total HSSI PMA TX Serializers	0
  Total PLLs	1 / 6 ( 17 % )
  Total DLLs	0 / 4 ( 0 % )
  
• ozpropdev Posts: 2,791

  2018-06-12 05:31

  And here's a build for a 512k hub P1V with PortB included (64IO)
  ALM usage jumps from 18% to 22%
  Based on Chip's comment that the Cordic uses ~8K ALM's that's about 20% of the available ALM's.
  A P2 build will come down finding a good balance of cogs and smartpins.
  

  Flow Status	Successful - Tue Jun 12 15:18:41 2018
  Quartus Prime Version	17.0.0 Build 595 04/25/2017 SJ Lite Edition
  Revision Name	top
  Top-level Entity Name	top
  Family	Cyclone V
  Device	5CSEBA6U23I7
  Timing Models	Final
  Logic utilization (in ALMs)	9,023 / 41,910 ( 22 % )
  Total registers	6485
  Total pins	74 / 314 ( 24 % )
  Total virtual pins	0
  Total block memory bits	4,358,144 / 5,662,720 ( 77 % )
  Total DSP Blocks	0 / 112 ( 0 % )
  Total HSSI RX PCSs	0
  Total HSSI PMA RX Deserializers	0
  Total HSSI TX PCSs	0
  Total HSSI PMA TX Serializers	0
  Total PLLs	1 / 6 ( 17 % )
  Total DLLs	0 / 4 ( 0 % )
  
• KMyers Posts: 433

  2018-06-12 15:51

  So it sounds as if the DE NANO 10 would make a minimal useable P2. Would not want to take Chips valuable time at this point of development but perhaps later esp after I re learn my way around Quartus again. Did build a P1 with additional memory years ago!