The New 16-Cog, 512KB, 64 analog I/O Propeller Chip

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Comments

  • cgracey wrote: »
    One of the male audience (almost everyone was male) raised his hand and asked why he ought to go to school there. The answer, from what I remember hearing from Ken, was more PC blather. It seems to me that political correctness has actually broken the requisite feedback loop needed to get more paying (borrowing) students into their engineering program.

    That sounds about right. It seems like it's every day that I hear another story about over-the-top PC peddling and caving in to absurd demands by PC extremists at a lot of universities in the West, with the US, UK and Sweden being notoriously bad about it. I see no way it can be tenable for very long.

  • Cluso99 wrote: »
    Chip,
    Very interesting info thanks Chip.

    I expect the 180nm & 350nm are used for the small standard chip parts which is why there is no need to shrink that process.

    This brings up an interesting option. I wonder what could be achieved in 350nm....
    a) A P1V ?
    b) A P2 without ADC and Hub RAM - use an external RAM ?


    I wonder if the second option (8 cogs) could be used to build a new P2 variant to prove the design while still giving us a usable mini P2.

    I thought the P1 was already manufactured on the 350nm process. If you made a P2 with external hub ram, you'd have to convert it to a P1 style hub instead of the eggbeater type with multiple ram slices.

  • cgraceycgracey Posts: 11,769
    edited 2015-08-16 - 00:19:05
    mark wrote: »
    As for IC fabrication, there seems to be little effort in directly reducing costs of existing cell sizes, with all the focus being on enabling smaller geometries, and eventually reducing prices as the processes grow long in the tooth and the fabs have long amortized the cost of their equipment. There's enough incumbents to support the industry as-is, so there's no need to make it cheap enough for the nobodies of the world to waltz in a fab and make their own chips. Then again, there's probably no better way of making equipment that's capable of producing ICs in a process equivalent to 20 year old tech. But what about 30 year old tech? Is there value in making, say, a 1um process available to the average nerdy Joe? Could the availability of modern technology make the necessary equipment "cheap" to manufacture? It's great that the hobbyist can now get a PCB produced and assembled on the cheap with access to plenty of free software development tools, but unfortunately producing ICs are still out of their realm despite the tech having existed for 40+ years. It really is one of the final frontiers for the electronics hobbyist. Hopefully that changes soon.

    I've been impressed that cell sizes are about as efficient as they could be, right out the door. They need smaller processes to fit more.

    Think about how little PCB's have changed in 30 years. They haven't even gone through one order of magnitude in density increase, while IC's have gone through maybe five or six! The tools needed to keep up with IC's are way beyond what PCB's require, in terms of development cost. That's why it just keeps getting further out of the average guy's hands. PCB tech is within the limits of hobby efforts, while IC tech is way beyond. If $500 prototypes were still available, that would not be so, though.
  • mark wrote: »
    I thought the P1 was already manufactured on the 350nm process. If you made a P2 with external hub ram, you'd have to convert it to a P1 style hub instead of the eggbeater type with multiple ram slices.

    The P1 is in 350nm.

    You're right about the hub ram needing to not be egg-beater style if it were external. It would take ~800 pins for external egg-beater memory, whereas P1-style would only need ~50.

    One other thing my friend told me about their big chips: They take 1 whole month to compile! The P2-Hot was taking ~1.5 hours. That's synthesis and place-and-route. He said that if they discover that changes are needed after a 1-month compile, they have a special engineer who can go into the layout and change things around - and if that guy died, they might as well quit trying to make chips.
  • jmgjmg Posts: 14,022
    cgracey wrote: »
    One other thing my friend told me about their big chips: They take 1 whole month to compile! The P2-Hot was taking ~1.5 hours. That's synthesis and place-and-route. He said that if they discover that changes are needed after a 1-month compile, they have a special engineer who can go into the layout and change things around - and if that guy died, they might as well quit trying to make chips.
    Wow, and that will not be on Desktops either !
    Still, they must be doing many sub-section builds before they launch the final 'Big Build', so that must be outside the iterative design loops.


  • Is the compiler and synthesizer capable of parallel processing?

    Amazingly, on big mechanical CAD models for example, there is no big iron speed up. The fastest desktop I could buy is kind of it. Geometry resolution and parametric computation is still single thread, unless one uses difficult and somewhat experimental techniques.

    As for that special guy... he needs to be mentoring somebody.
    Do not taunt Happy Fun Ball! @opengeekorg ---> Be Excellent To One Another SKYPE = acuity_doug
    Parallax colors simplified: https://forums.parallax.com/discussion/123709/commented-graphics-demo-spin<br>
  • potatohead wrote: »
    Is the compiler and synthesizer capable of parallel processing?

    Amazingly, on big mechanical CAD models for example, there is no big iron speed up. The fastest desktop I could buy is kind of it. Geometry resolution and parametric computation is still single thread, unless one uses difficult and somewhat experimental techniques.

    It's crazy to think that some of the most compute-intense applications which could use all the speedup they could get have not been or are unable to be parallelized despite parallel processing having existed for a long time.

    "... they have a special engineer who can go into the layout and change things around - and if that guy died, they might as well quit trying to make chips."

    That's troubling, though I couldn't help but to laugh. Something happens to a single engineer or he quits, and the company, which presumably isn't small, has to close up shop! It's so absurd that it's funny.
  • Yeah, crazy isn't it?

    In the case of geometry kernels, they are just huge, seriously complex and not easy to reproduce. Millions of man hours in those things.

    And there are dependancies in the data. We are very slowly working to refactoring those things, and build big models differently, but it just isn't easy.

    I have a couple that I have managed to get optimized. But to take advantage of them, I need to run many copies of the app and play traffic cop. Worth it though. Sometimes it can mean an order better performance. Doing this is non obvious. Vendors are very slow to think about it too.

    Just wondered what the state of these synthesis tools is. If it is like geometry engines, good luck!
    Do not taunt Happy Fun Ball! @opengeekorg ---> Be Excellent To One Another SKYPE = acuity_doug
    Parallax colors simplified: https://forums.parallax.com/discussion/123709/commented-graphics-demo-spin<br>
  • cgracey wrote: »
    They take 1 whole month to compile!
    Yikes! I will never complain about Quartus compile times again.

    Melbourne, Australia
  • Mosis no longer publish multi-project-wafer price list, but there are others that still do:

    http://www.cmc.ca/WhatWeOffer/Make/FabPricing.aspx
    http://cmp.imag.fr/products/ic/?p=prices
    http://www.europractice-ic.com/docs/MPW2015-general-v6.pdf

    Will a P1 verilog fit in a 1.25mm2 STM 28nm FD SOI design?

    https://www.cmc.ca/WhatWeOffer/Products/CMC-00200-02843.aspx

    "1. STMicroelectronics prohibits use of this 28-nm technology for any medical or military applications." No problemo.

    "2.The expected number of chips to be delivered for this technology is 30." 30 dies (28nm) for $4,000? WTF, $133 per die. Wasn't that funny?

    It is just $4,000 peer reviewed price for canadian academic. Is there any EE canadian student here? Who volunteers to join a EE course to make a P1V into 28nm?. Is Parallax ready to deal?

    ---

    Chip, CMC still list 350nm at $175/mm2 for a mimimum 1.1mm2 design (through MOSIS). And $550 for 350nm AMS (through CMP):

    http://www.cmc.ca/~/media/WhatWeOffer/Documents/Product Catalogue Fall 2014.pdf

    Thought it is one year old pricelist (v4.0 Sep 2014).
  • About external RAM,

    Altera MAX 10 allows the use of external DDR2 (only those versions with more than 16,000 Logic Elements; BGA 256/324/484 packaging; and -6 o -7 speed).

    You still can use the internal FPGA block ram for COG RAM, and the external DDR3 (or LPDDR) for HUB RAM. This way you will solve a lot of issues. By using a small FPGA (16,000 to 50,000 LE FPGA) you will be sure that:

    - your design will use less die space (mm2),
    - the final IC price will be cheaper (thousands of ICs inside a wafer),
    - we can use commodity ddr2/lpddr IC for hub ram IC ($3),
    - hub ram will be several MB instead of KB,
    - complete system will still be low power (even with two ICs),
    - threehouse will not need to buy a expensive license,
    - compile times for a small FPGA will take less time,
    - the fpga development board will be cheaper,
    - having small number of LE will force you to Keep It Simple,

    ... and you can always get more clever with your verilog ;-D

    I think a small FPGA or big CPLD, is a good idea. Even if you don't plan to use DDR RAM. I remember a post were you said that having limited resources make you push the limits earlier. Thanks for the update !
  • jmgjmg Posts: 14,022
    Ramon wrote: »
    You still can use the internal FPGA block ram for COG RAM, and the external DDR3 (or LPDDR) for HUB RAM. This way you will solve a lot of issues.

    .. but create many more issues too.
    DDR3 needs LVDS, and MHz figures that are not really 180nm ball-park, and DRAM has latency issues that would lower determinism, and increase sw-cross-talk, both of which are key Prop feature areas.
    Other vendors are taking a stacked die approach, which avoids a pin bottleneck, and does make it nominally single chip (but does impose other compromises ).
    Nuvoton has a new ARM with 2MB of SPI Flash, as 2nd Die, as they see CODE storage as more important that Data in the MCU space. SPI flash has lower connection costs than SDRAM.

    Ramon wrote: »
    - the final IC price will be cheaper (thousands of ICs inside a wafer),
    The memory is under 40% of the die area, so the savings are not nearly as large as you imagine.
    The PCB cost and design costs of always having to add memory takes this away from an easy to use, single chip device and into a quite different market space.

    Smarter than forcing external SDRAM, would be to allow optional XIP from cheap Serial Flash memory.

  • jmg, forget about the DDR RAM.

    What you said is true, I'd prefer not to add another IC (and P2 in DIP-40 packaging). The important thing is to use a small FPGA (or big CPLD ;-)

    I just was trying to make a joke (in response to Chip post where he said "you can always get more clever with your programming).
  • mark wrote: »
    So how many people would want to run a high-tech business that isn't making millions of $ a year?

    In a way, I have.. for over 25 years..
  • Mark,
    So how many people would want to run a high-tech business that isn't making millions of $ a year?
    Oddly enough thousand, maybe millions of people do. They can be employing very sophisticated "high-tech" in their very small businesses. Most of them you have never heard of but supply their skill and services to the names you have.

    Many of them are happy to make a living doing what they enjoy and interests them. I would suggest Parallax is such an example. Growing big, making tons of money, getting into IPO's etc etc is not what drives them. Not to say that they would say no to a bigger market and more income though.

    I guess it depends on what you mean by "high-tech". Certainly there are few options for starting a chip foundry now a days unless you have a few billion to spend.

    What would be cool in the chip industry now is if they could figure out away for the small guys to get their designs made. As a student, hobbyist or small company I should be able to knock up a circuit description in VHDL, Verlog or whatever and get it made in small quantities for a few hundred bucks. Like we can for PCB's now. Somehow these chip giants need to be able to mix and match a thousand different designs on to a single wafer rather than making tens of thousands of the same thing.

    Imagine that, write your HDL, test it on your FPGA, uploaded to the Global Foundries, or whoever, web site and get a reel of chips back a month later. Free postage from China of course :)

    With that in place we would then have the hardware equivalent of Open Source software. People and companies around the world could collaborate on massively complex designs and get them made, iterating the design again and again. Think the semiconductor equivalent of the Linux kernel or whatever.
  • Heater. wrote: »

    I guess it depends on what you mean by "high-tech". Certainly there are few options for starting a chip foundry now a days unless you have a few billion to spend.

    What would be cool in the chip industry now is if they could figure out away for the small guys to get their designs made. As a student, hobbyist or small company I should be able to knock up a circuit description in VHDL, Verlog or whatever and get it made in small quantities for a few hundred bucks. Like we can for PCB's now. Somehow these chip giants need to be able to mix and match a thousand different designs on to a single wafer rather than making tens of thousands of the same thing.

    Imagine that, write your HDL, test it on your FPGA, uploaded to the Global Foundries, or whoever, web site and get a reel of chips back a month later. Free postage from China of course :)

    With that in place we would then have the hardware equivalent of Open Source software. People and companies around the world could collaborate on massively complex designs and get them made, iterating the design again and again. Think the semiconductor equivalent of the Linux kernel or whatever.

    I did mean something as high-tech as operating a foundry which would require a non-negligible amount of capital to start up and run, or at least substantially more than a small software or hardware engineering house. You're right - modern high-volume fab costs billions to develop. When we're talking about that kind of money, there's little opportunity to cater to the hobbyist. Even if one could get some equipment on the used market, it wouldn't be cheap by any means, and as the machines get old, the manufacturer will stop supporting them so when they break, you're SOL. That's why I think it would be important for such a company to at least develop their own low feature density lithography machines.

    Companies like MOSIS do offer multi-project wafers, but I'd have to imagine that it's still not cheap. Everyone has to get paid, so MOSIS for their services (including masks?), the fabs, and everyone (if anyone) in between whoever they may be. The cheapest method generally tends to be dealing with a company that is vertically integrated, and caters to a certain market.

    Unfortunately, I think we're still very long ways off from hobbyists being able to get their own designs manufactured on a modern process.

  • So, the whole semi-conductor fab business is big and expensive.

    One could compare it to building skyscrapers or bridges or tunnels or highways or Jumbo Jets. None of us could finance a tunnel from England to France, for example, but it got built and anyone can use it pretty cheaply.

    All we need is a way to ride for cheap on the chip fab mega investment.

    There is some evidence to suggest this possibility is on the tables. For example the guys involved in the RISC V CPU architecture point out that there are many start ups, with all kind of ideas, that are desperate to get away from having to licence an ARM or MIPS CPU core before they can get started.

    I know nothing of chip design but I'm going to propose that it is only a matter of software away.

    Basically a chip fab stamps out images on silicon. To grossly simplify. Those images get sliced up and packaged. There is your device.

    All it needs is a means to stamp out many different designs on the same wafer as and when required.

    With a pile of Free and Open Source blocks, like the RISC V CPU core and thousands of others, companies could find it's cheaper to put everything they want on their own chip rather than design with separate devices and printed circuit boards.
  • But in the case of a bridge or tunnel, it was designed for passage of individual vehicles. You could say it has more similarities to a railway where you simply can't just put your own locomotive on it and go. With enough money, you can put a shipping container on a train, but if you don't have enough stuff to fill it with then it may not be a cost effective proposition. What you're suggesting is a means to get various parties to load up the container and split the cost. MOSIS and probably some others do this, but I'd imagine it somewhat complicates the logistics and possibly requires all the die to be the same size. And I'm not sure this addresses extremely small runs (say < 10) where setup time might be costly and inconvenient for the fab.

    If there is a hobbyist market for having their own ICs fabricated in very low quantities, I'd imagine it's very small. Unfortunately this makes it a very unattractive proposition for fabs that have the capability of pumping out millions upon millions of ICs a year. Money talks, but that's out of the realm of just about all hobbyists.

    Smallish companies do have various options as history has shown, but that doesn't get me or you any closer to having our bug-riddled die sent to our home mailbox :)
  • Hey, there you have it. The container idea.

    The semiconductor equivalent of containers. Every chip is the same size and shape. Same I/O. They all end up in the same package. There might be full size, half size options. Give us whatever crap you want to put in there as long as it fits the container.

    I'm betting this is only a software tool tweak away.

    Surely it's not going to help hobbyists in the same way as we don't normally make use of shipping containers. But it might help the flow of work among many small players.

    I know, just dreaming...
  • jmgjmg Posts: 14,022
    Heater. wrote: »
    ...companies could find it's cheaper to put everything they want on their own chip rather than design with separate devices and printed circuit boards.

    Sure, they do that already. The problem is that threshold is getting ever-higher, and for all the others, we have FLASH MCUs and FLASH FPGAs - and there, the solutions are 100% software - you buy a part and download the code to do what you want it to.
    FPGA volumes are climbing, in part because of the high costs of full-custom.
  • My experience with FPGA is limited. More than two decades ago I was involved in a project that demanded an ASIC. We had what seemed like half a work bench covered in very expensive boards carrying FPGAs that was being used to develop, test and verify the HDL. My only input to that effort was to make sure the guys designing it understood the inputs and delivered the outputs correctly.

    That was of course small fry by today's standards, that whole design could have been built with a couple of handfuls of TTL chips.

    So, jmg, you have a point. The cost of chips has sky rocketed and the FPGA is that "container" I was talking about above. Becoming more and more economical for the small guy. They were really expensive back then.

    Heck, I have here a Parallella board with ARM CPU Zynq FPGA and 16 core parallel processor. If only I could figure out what to do with it....

  • While its great to think how much you can get a 350nm run done for, that does not include...
    1. The cost to convert the Verilog to a Mask
    2. The packaging of the die into chips
    and there are probably other costs too.
    Then what happens when it doesn't work! You will have no idea what is wrong.

    However, perhaps a service like MOSIS that uses a standard size die and puts that into say a QFP64 or a QFP84 might be a nice job.
    While I am sure a number of hobbyists and commercial users would love this, there probably just isn't the motivation for companies to do it :(

    Even OpenCores haven't been able to get their ASIC off the ground.
    My Prop boards: P8XBlade2 , RamBlade , CpuBlade , TriBlade
    P1 Prop OS (also see Sphinx, PropDos, PropCmd, Spinix)
    Website: www.clusos.com
    P1: Tools (Index) , Emulators (Index) , ZiCog (Z80)
    P2: Tools & Code , Tricks & Traps
  • Cluso,

    When you say Opencores ASIC I presume you mean the OpenRISC ASIC initiative.

    That may well have fizzled out.

    However the OpenRISC is basically the DLX architecture from Berkeley.

    Those Berkeley guys have moved on to the RISC V which is gaining a lot of traction around the world.


  • cgracey wrote: »
    Think about how little PCB's have changed in 30 years. They haven't even gone through one order of magnitude in density increase, while IC's have gone through maybe five or six! The tools needed to keep up with IC's are way beyond what PCB's require, in terms of development cost. That's why it just keeps getting further out of the average guy's hands. PCB tech is within the limits of hobby efforts, while IC tech is way beyond. If $500 prototypes were still available, that would not be so, though.

    Thinking about this, I don't know if it's a fair comparison. It you think about PCBs more generically (as a circuit design, not just as traces on fiberglass), it has gone through several iterations.

    First, an increasing number of common circuit elements have moved from relatively large discrete components to significantly smaller integrated packages. You don't build a timer circuit any more; you use a 555. You don't build an amplifier circuit, you use a LM386. While these ICs aren't technically what we call a PCB, they are functionally equivalent (just in a much tighter package).

    Second, SMDs have allowed for much smaller designs. Okay, sometimes the size of the PCB (the fiberglass) doesn't change as much as the component density does. And with increased density has also come increased numbers of board layers, hidden vias, etc. I think a side-by-side comparison of a SMD laden PCB and older variants would certainly make one feel that PCBs have changed over the years

    Now, if we are strictly talking about the fiberglass and copper traces, then I agree that it hasn't really changed that much. But it hasn't needed to either. For that matter, it probably shouldn't change that much. The vast majority of us live and work in a macroscopic world, which is where the fiberglass/copper also lives. Where it gets expensive is when we have to work in the microscopic world, where IC design also lives. Humans are just not precise enough for working at that level, so we have to use machinery to do it. And there is where the cost comes in. Heck, even the use of SMDs (0402! or even 1608!) shows this to be the case, as it's an order of magnitude more expensive to have an oven, solder paste, solder stencils, etc. as compared to a soldering iron and some solder.
  • Yanomani wrote: »
    Hi Chip

    By reading former posts, focusing on total gate count used by the actual design, versus 300 k max, allowed by the synthesis tools licensing terms, are there any chances for the gate count that will be allocated to the smart pin logic design, added to the ones already in use, to exceed the limits?

    Henrique

    It's possible that smart pins could blow us past 300k gates. Every pin needs at least some form of a smart pin circuit just to configure the DACs, ADC, logic mode, etc.
  • User Name wrote: »
    Chip said: " I don't think these older technologies are going away for a long time."

    A neighbor who works for a power semiconductor company (that everyone has heard of) told me that virtually all of their devices are implemented with 350nm rules. There is not even a discussion about changing that.

    Analog needs large depletion regions in FETs, with many dopant atoms, in order to operate nicely. Plus, as things get smaller, device-to-device mismatch increases. For these reasons, analog needs to be BIG, and doesn't benefit from perpetual process shrinkage like digital does.
  • jmg wrote: »
    cgracey wrote: »
    One other thing my friend told me about their big chips: They take 1 whole month to compile! The P2-Hot was taking ~1.5 hours. That's synthesis and place-and-route. He said that if they discover that changes are needed after a 1-month compile, they have a special engineer who can go into the layout and change things around - and if that guy died, they might as well quit trying to make chips.
    Wow, and that will not be on Desktops either !
    Still, they must be doing many sub-section builds before they launch the final 'Big Build', so that must be outside the iterative design loops.

    I think the problem is that with linear increase in gate count, placement and route permutations go up exponentially.
  • ozpropdev wrote: »
    cgracey wrote: »
    They take 1 whole month to compile!
    Yikes! I will never complain about Quartus compile times again.

    I realize now that my initial trouble with long Quartus compile times on the Cyclone V was because it was not inferring regular RAM from my Verilog code, but making a huge fliplop/mux mess because it thought some special case was being asked for. After I got the straightened out, it was as fast as compiling for Cyclone IV.
  • cgracey wrote: »
    ozpropdev wrote: »
    cgracey wrote: »
    They take 1 whole month to compile!
    Yikes! I will never complain about Quartus compile times again.

    I realize now that my initial trouble with long Quartus compile times on the Cyclone V was because it was not inferring regular RAM from my Verilog code, but making a huge fliplop/mux mess because it thought some special case was being asked for. After I got the straightened out, it was as fast as compiling for Cyclone IV. Single-cog compiles are now taking only 3 minutes and 38 seconds, which is nothing. It takes about as long to just download the resultant image to the DE2-115 board. Sometime soon I will switch to our Cyclone V -A7 board (the -A9's are on the way).
  • cgraceycgracey Posts: 11,769
    edited 2015-08-17 - 16:27:41
    Ramon wrote: »
    Mosis no longer publish multi-project-wafer price list, but there are others that still do:

    http://www.cmc.ca/WhatWeOffer/Make/FabPricing.aspx
    http://cmp.imag.fr/products/ic/?p=prices
    http://www.europractice-ic.com/docs/MPW2015-general-v6.pdf

    Will a P1 verilog fit in a 1.25mm2 STM 28nm FD SOI design?

    https://www.cmc.ca/WhatWeOffer/Products/CMC-00200-02843.aspx

    "1. STMicroelectronics prohibits use of this 28-nm technology for any medical or military applications." No problemo.

    "2.The expected number of chips to be delivered for this technology is 30." 30 dies (28nm) for $4,000? WTF, $133 per die. Wasn't that funny?

    It is just $4,000 peer reviewed price for canadian academic. Is there any EE canadian student here? Who volunteers to join a EE course to make a P1V into 28nm?. Is Parallax ready to deal?

    ---

    Chip, CMC still list 350nm at $175/mm2 for a mimimum 1.1mm2 design (through MOSIS). And $550 for 350nm AMS (through CMP):

    http://www.cmc.ca/~/media/WhatWeOffer/Documents/Product Catalogue Fall 2014.pdf

    Thought it is one year old pricelist (v4.0 Sep 2014).

    That is all very interesting! It looks like they're all Canadian or European.

    I requested commercial pricing from CMC for the 28nm process. I saw on CMP's site that you can get a 1.88 x 1.88 mm 28nm chip made for Euro 36,000, which isn't bad. That would have to be digital pins, only.

    Thanks for posting this info.

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