P2D2 - An open hardware reference design for the P2 CPU

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  • Cluso99Cluso99 Posts: 13,786
    edited June 19 Vote Up0Vote Down
    I use a Pair of jewellers eyepiece. (my brother was a jeweller so he gave me his pair) They are almost like goggles with a strap around your head. They go over my glasses. They give an excellent closeup view of the ic pins. Don't bother with the eBay magnifying glasses with the led lights - they are rubbish.

    If we get an OSH stencil made up I can screen, place and solder in my reflow oven. It does a fantastic job - it ought to as it was $5K. I will do my own boards too, provided I come up with a different design. Currently tho there seems little that I would want to change from Peters design :)
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  • My compliments on a very nice looking and well thought out board Peter. Is there any way to have a separate the Chip Select signal going to the SD /CS pad on the bottom of the board so that two SD cards (one internal for code, one externally accessible for logging data) can be used.
    In science there is no authority. There is only experiment.
    Life is unpredictable. Eat dessert first.
  • T ChapT Chap Posts: 3,790
    edited June 19 Vote Up0Vote Down
    Nice 3D! If you don’t have a stencil then imo the next best thing is to find some very fine pitch solder and tin each pad with a fine tip pencil. Then with tweezers hold each part on the pads and use air. This is very easy and fast. For the prop2 place it on the tinned pads and then use air. This is much easier than a pencil for the prop too. Rework stations are 100$. The thing about a stencil is you really need a solid stencil printer and framed stencil to consitentaly and reliable put paste on fine pitch stuff like .5mm pitch tQFP especially for a batch of boards. The cheap prototype non framed stencils are a pain for fine pitch if you are running a number of boards. I’m sure when the ic is ready I’ll make a test board and can run multiples on a machine to have available if needed.
  • roglohrogloh Posts: 653
    edited June 20 Vote Up0Vote Down
    Mock up looks very cool.

    Will it be easy to cut off the sides and use a castellated version of the board? Does anything special need to be done during board manufacture to enable that, or is it just a matter of carefully scoring along the 0.05 inch holes and snapping off? I've never made a board in that way to know how well it works. I guess the thinness of the PCB helps though it is a long narrow section to be broken off and ideally in one go. Load into a flat edged vice and bend it?
  • Peter JakackiPeter Jakacki Posts: 7,584
    edited June 20 Vote Up0Vote Down
    What I usually do with protos is a mini-panel especially when the pcbs are tiny so they can be assembled easily and even a manual stencil can be registered if the edges of the panel has holes to match the stencil. This is what I would prefer and I will have to see if that is still a cheap option with these places. If the board is v-grooved it makes it a easy to just snap them apart from the panel but I wonder if I could do something to a lesser degree with the castellations. Maybe if I put all my tracks to the pin headers on the bottom side then it wouldn't matter if it were half v-grooved......

    Otherwise a guillotine press would do the job.

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  • jmgjmg Posts: 11,778
    rogloh wrote: »
    Will it be easy to cut off the sides and use a castellated version of the board? Does anything special need to be done during board manufacture to enable that, or is it just a matter of carefully scoring along the 0.05 inch holes and snapping off? I've never made a board in that way to know how well it works. I guess the thinness of the PCB helps though it is a long narrow section to be broken off and ideally in one go. Load into a flat edged vice and bend it?

    If you were serious about using edge/SMD mounting, you would route the PCB edges in the PCB FAB.
    A snap-in-the-vice is going to stress the copper significantly, & the tear-apart becomes a lottery, so using a fine toothed saw + file would be a less-stress one off solution.


  • T ChapT Chap Posts: 3,790
    edited June 20 Vote Up0Vote Down
    I make panels 12”x14” and have many boards on it. Put a .05” space between all boards and create a rectangle on the silk for each board. Then use this carbide grit blade on this Rockwell saw(basically an upside down jigsaw) that is dedicated to cutting pcb’s. I use a spray bottle and flood the board and blade at all times so there is not dust. Typically I don’t do anything to the board after but I do have a belt sander I may use sometimes if needed to smooth out the board, using water sprayed on the belt. I don’t like stressing a board much bending it to break it. This saw method works perfectly and the sander can clean it up nicely.

  • You will find that trying to hand solder fine pitch simply with a very fine tip can be a very frustrating experience since the fine tip will not conduct sufficient heat to the mass of pad and pin and solder. If I have to hand solder fine pitch I will tack the component down first and then blob on fresh solder "across" all the pins with a warm iron, hot enough to make it blob but not hot enough to burn off the flux. I then turn up the iron, wait until it's hot, and then holding the pcb at an angle I run the broad flat tip along the pins letting the solder melt properly and balling onto the tip as I run it down and veer off at the last pad with the blob of solder on the tip (watch your bare legs). If some pads are bridged, no problem, run the flux gel down the pins and with a clean tip repeat the exercise and you will have a row of very neat and cleanly soldered fine pitch pins. The mass and shape of the broad flat tip helps to hold and conduct the heat as well as attract and hold the mass of excess solder. Easy peasy.


    Peter,

    Very nice design. But how do you hand solder the ground pad?
    Sapphire
  • If you intend to use the castellation option to directly solder the board over another one, perhaps adding an outer line of smaller-diameter, unplated holes, to the .05" pitch one (as in the following link, type 2 option), the chances to peel-off plated vias tubbing, or even connected tracks, due cut-process induced stresses, would be less likely to occur.

    https://prototypepcb.com/castellated-holes/

    The option to assemble some extra ceramic caps to the underside of P2 board will be lost, tought, so would worsen heat dissipation too, unless you cut a window at the "mother" board, to partly recover the usefullness of these features.
  • jmgjmg Posts: 11,778
    Yanomani wrote: »
    If you intend to use the castellation option to directly solder the board over another one, perhaps adding an outer line of smaller-diameter, unplated holes, to the .05" pitch one (as in the following link, type 2 option), the chances to peel-off plated vias tubbing, or even connected tracks, due cut-process induced stresses, would be less likely to occur.

    Interesting approach - they seem to rely on drill being 'cleaner' than edge route. Not so easy to hand solder ?

  • roglohrogloh Posts: 653
    edited June 20 Vote Up0Vote Down
    jmg wrote: »
    If you were serious about using edge/SMD mounting, you would route the PCB edges in the PCB FAB.
    A snap-in-the-vice is going to stress the copper significantly, & the tear-apart becomes a lottery, so using a fine toothed saw + file would be a less-stress one off solution.


    Yeah that was what I was sort of worried about too. Unless designed for snapping, it may well become a bit of a lottery to do so in a vice. Otherwise careful file/Dremel perhaps? I guess I could always work with those DIL 40 way headers if its ever required to embed this reference board into something as a prototype, though mating board to board via the castellation approach would be rather nice too as it could result in something quite slim and compact.

    Perhaps even adding some non plated micro sized holes between the 0.05 holes could assist the snapping? Though it may weaken the board a bit too.
  • If the pcb is thin enough it is easy enough to cut this with a normal paper guillotine or good quality shears. I tried both approaches and found the guillotine very easy. I don't see any problems with this approach.

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  • Great, that result looks reasonable and still solderable. Lining it up straight in the guillotine will become the thing to deal with. :smile:
  • I found with a light background I could see through the holes and the trick was not to aim for the center but almost all the way. I'm sure if I took another shot at it the results would look better. The guillotine btw is just a cheapie as the better ones have a very sturdy sure n certain cutting arm.

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  • Finally too, the proof of the pudding, how does this method solder up?

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  • Was just looking at your schematic again Peter and noticed something I didn't realise before. Was the intent of the red LED to show SD/Flash activity directly off the output lines from these devices using pin 58, or for driving the LED independently from the Prop when both these devices are deselected? If it's for an activity LED the actual drive and LED brightness is going to be data dependent in that case and would only light up during binary 1's being output. I'd normally use the SD CS signal to light LEDs to show when the SD is active but I guess on your board that type of approach may not be possible due to the latest P2 pullup/pulldown requirements for SD/Flash boot choice etc? SD clock may be another option for LEDs (50% duty cycle when lit) but it is also the CS signal for the flash if that mattered. I wonder if P59 is a better choice so as not to load the SD card with mA of load and also being directly driven out from the P2...

    Am looking for that latest documentation from Chip to see how the latest and greatest pullup/pulldown boot scheme worked but can't seem to find it :-(
  • roglohrogloh Posts: 653
    edited June 20 Vote Up0Vote Down
    So if this is the current pullup scheme from Cluso's first post in this thread...

    http://forums.parallax.com/discussion/168502/p2-rom-booter-serial-flash-sd-card-monitor-and-taqoz-features-and-operation

    then perhaps an activity LED from 3.3V through a resistor to pin 61 would be a good choice? It's the Flash CS pin and would be the SCLK of the SD card. When idle high it would not be lit but when either the flash CS or SD is accessed it would light up at half brightness for SD and full brightness for flash during all accesses.

    Seems like soldering an LED from pin 6 to pin 8 on your serial header will achieve the same result for an activity LED too by the way - happy coincidence?
  • Peter JakackiPeter Jakacki Posts: 7,584
    edited June 21 Vote Up0Vote Down
    @rogloh - The 1.5ma drive is not a problem for any device but I had to move my LEDs out of the way of the serial connector and in the process found a way to sink it from P61 instead. All I really want is an LED to show boot activity and also programmed status blinks.

    As for hand soldering, I would still use solder paste for the main pad but rely on heating the bottom side since the whole area under the chip has the solder mask exposed.
    If you don't have solder paste you could always drill out the center hole and take your chances with the iron.

    Here's the latest - the P2D2 document has been updated with the schematics etc

    P2D2-TV-180621.png

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  • Peter JakackiPeter Jakacki Posts: 7,584
    edited June 25 Vote Up0Vote Down
    There have been some very minor changes to the artwork and the main difference is that the RESn signal has been moved from pin 1 of the A connector to pin 1 of the B connector so that it is next to the boot signals. This is so that when P2D2 is plugged into a pcb or matrix board, the boot connections are all in one place. The bottom solder mask is exposed for the thermal area under the P2 chip as well as the switching regulator plus I like to have a block fill on an overlay for marking purposes. The top solder mask is not shown in these shots but of course the P2 pad is exposed. Maybe I might put a big P2D2 label on the bottom overlay in case this pcb is ever mounted upside down, as it could very well be since it makes it a lower profile if low profile pin headers are used.

    If I don't make any other changes then I will submit this pcb on Tuesday and get a run of around 10 boards on 1mm pcb just for evaluation of the layout and circuit.

    P2D2D-TV.pngP2D2-BV.png
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  • Here are the gerbers I will need to submit. Maybe someone can check them to see if everything is in order as I normally only submit Protel files.

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  • Hi Peter Jakacki

    One of the rectangular solder pads, at the center of the uSD card, seems to be different from the other ones. Is it expected?

    Henrique
  • jmgjmg Posts: 11,778
    edited June 25 Vote Up0Vote Down
    Here are the gerbers I will need to submit. Maybe someone can check them to see if everything is in order as I normally only submit Protel files.

    The two Gerber Viewers I checked with, show the pin headers as octagonal, but rotated with points at 12 O'Clock, 3 O'clock etc (so not the same as your image above) the spun points reduce the copper clearances.
    There are 2 little spurs on U1 that could trigger a question from the FAB.

  • I'm using Kicad (R10571 nightly build) Gerber Viewer.

    The clearance between P54 land pattern and the via that conects V5254 to 3.3V also seems to be too small to avoid solder bridging.
  • I've had that issue with Rotated octagonal pads before. I couldn't work out whether it was "just me" - I just avoided them ever since.
  • BTW, The board was laid out using 8mil/8mil rules but since 6/6 is what the PCB house can fab I have relaxed the clearance for the copper pours to 7mil. It passes DRC and manual checks too.

    @Yanomani - I checked P54 but clearances were fine and also the same in my gerber viewer (Gerbv 2.6.1).
    Here's what the top layer looks like in the gerber viewer and in Protel.
    P2D2D-GTL.pngP2D2D-TL.png
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  • jmgjmg Posts: 11,778
    edited June 25 Vote Up0Vote Down
    Tubular wrote: »
    I've had that issue with Rotated octagonal pads before. I couldn't work out whether it was "just me" - I just avoided them ever since.
    Looking like a good move..

    I can find this spec for polygons :

    P Indicates that this is a polygon aperture
    <Outer diameter> Diameter of the circumscribed circle, i.e. the circle through the
    polygon vertices. Must be a decimal > 0
    <Number of vertices> Number of polygon vertices, ranging from 3 to 12
    <Rotation> A decimal number specifying the rotation in degrees of the
    aperture around its center
    Without rotation one vertex is on the positive X-axis through the center. Rotation angle is expressed in decimal degrees;
    positive value for counterclockwise rotation, negative value for clockwise rotation
    <Hole diameter> Diameter of a round hole. If missing the aperture is solid
    See section 4.11.4.5 for more details.
    The hole modifier can be specified only after a rotation angle;
    set an angle of zero if the aperture is not rotated.


    Looks like a bug in Protel99.

    Editing the line to the below (I added the optional hole, to confirm I had the right pad)
    %ADD48P,1.727X8X22.5X0.50*%
    renders ok on http://www.gerber-viewer.com/
    Looks like KiCVad GerbView has a bug in missing angle/circle.
  • jmgjmg Posts: 11,778
    @Yanomani - I checked P54 but clearances were fine and also the same in my gerber viewer (Gerbv 2.6.1).
    I think that comment related to that via being the closest to the pads, and the solder masks overlap, looks 'legal' but not as clean as the other vias, with separate clean circles.

  • On Semi and I were looking at some document that showed how to hook up an exposed-pad like the P2 has.

    A via array of maybe 6 x 6 vias must be built under the exposed pad. The via array carries the heat to a ground plane layer, preferably the bottom-most layer of the PCB, which is maybe 4 square inches, total.

    This arrangement enables dissipation of a few watts, in order to keep the junction temperature low. It is imperative that the via array connect solidly to a big ground plane.

    I can't find the document we used, but this was the setup that enables maximum power dissipation which was used to qualify the thermal design.
  • jmg wrote: »
    I think that comment related to that via being the closest to the pads, and the solder masks overlap, looks 'legal' but not as clean as the other vias, with separate clean circles.

    Exactly, that was the reason I've spoted it.
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