Multiplexing a DS1620 (temp) with a TSL230 (light)

I wanted to be able to measure temperature and ambient light with the Spinneret, but I didn't want to use pins A28..A31 on the daughterboard connector, which left only four: A24..A27. It turns out that it's very easy to multiplex these two chips together. The /OE pin on the TSL230 tristates the frequency output when high. The /RST pin on the DS1620 tristates DQ when low. So, by connecting /OE to /RST and OUT to DQ, I'm able to multiplex the two chips. That leaves CLK, which I connected to S1, as shown here:



I tied S0 high and S2 and S3 low. That gives me the maximum clock rate output, with a selection between 1X and 100X gains -- and a pin left over, which I could have used to control S0.

Here's a scope trace of a reading from the DS1620 amidst the frequency output from the TSL230:



Here's the Spin program that reads both:

CON

  _clkmode      = xtal1 + pll16x
  _xinfreq      = 5_000_000

  nOE           = 24
  nRST          = 24
  OUT           = 25
  DQ            = 25
  S1            = 26
  CLK           = 26

OBJ

  sio           : "FullDuplexSerial"

PUB  Start

  sio.start(31, 30, 0, 9600)
  ctra := %01010 << 26 | OUT
  frqa := 1

  dira[nOE]~~
  dira[S1]~~

  'configDS1620     'Only needed once, since it writes to EEPROM.

  startDS1620

  repeat
    sio.str(string("Light: "))
    sio.dec(light_sensor)
    sio.str(string(13,"Temp:  "))
    sio.dec(temp_sensor)
    sio.str(string(13, 13))

PUB light_sensor | time

  outa[nOE]~
  outa[S1]~~
  waitcnt(time :=  cnt + clkfreq / 1000)
  result -= phsa
  waitcnt(time += clkfreq / 10)
  result += phsa 

PUB temp_sensor

  outa[CLK]~~
  outa[nRST]~~
  wrDS1620($aa, 8)
  result := rdDS1620(9) * 9 / 10 + 32
  outa[nRST]~

PUB startDS1620

  outa[CLK]~~
  outa[nRST]~~
  wrDS1620($ee, 8)
  outa[nRST]~

PUB configDS1620

  outa[CLK]~~
  outa[nRST]~~
  wrDS1620($0c, 8)
  wrDS1620($02, 8)
  outa[nRST]~

PUB wrDS1620(value, bits)

  dira[DQ]~~
  repeat bits
    outa[DQ] := value & 1
    value >>= 1
    outa[CLK]~
    outa[CLK]~~
  dira[DQ]~

PUB rdDS1620(bits)

  repeat bits
    outa[clk]~
    result := (ina[DQ] << bits + result) >> 1
    outa[clk]~~

-Phil