Need help with Prop. Video Generator Unit (VGU)

Comments

• potatohead Posts: 10,267

  2011-01-06 08:42 edited 2011-01-06 08:42

  Well, I normally get PLLA configured right away. It takes time to settle.
  
  Also, how did you calculate the frequency? You need to put in a value that when accumulated at speed = equals your desired frequency.
  
  Try (desired_frequency / clockspeed) << 32
  
  Basically, the counter will be incrementing each clock cycle. You want the period of those increments to roll over the 32 bit counter register at your desired frequency.
  
  The more ones you have in that value, the more "jitter" you will have in the output. It's not a bad idea to round to closest value, keeping the number of "1" digits to a minimum, because of that.
• ericball Posts: 774

  2011-01-06 08:48 edited 2011-01-06 08:48

  I'm fairly certain your problem is with the counter configuration. You have FRQA = 80M which yeilds an output frequency (at 80MHz) of 80M / 2^32 * 80MHz = 1.49MHz, which is outside the PLL's 4-8MHz capture range (for a x16 VCO output of 64-128MHz). For a 80MHz VCO you need a 5MHz input so FRQA = 2^32 * 5MHz / 80MHz = 268,435,456 = $1000_0000.
  
  Also, the PLLDIV of /4 will give you a pixel clock of 20MHz and therefore a 10MHz square wave.
• homosapien Posts: 147

  2011-01-06 11:45 edited 2011-01-06 11:45

  Thanks for the insight, this is helping a lot. I now understand that the counter PLL's still run off the system clock the counter output (in this mode) mirrors PHS bit 31 .
  
  So I added to my code, and am now also activating the second counter (CTRb) as a NCO single-ended, using the same timing parameters as the VGU. I put in $1000_0000 for both FRQa/b, and the output from CTRb (pin0) is as expected, 5MHz (per the formula PHS[31] freq. = clkfreq*FRQregister/2^32)
  
  However, the output from the VGU is (with divider set to 1/4) 10MHz as Eric says. I would have expected 5MHz/4 =1.25MHz. I know I am being somewhat obtuse here, but what am I missing? New code (adding CTRb) shown below.
  
  Thanks again,
  
  -h
  
  

  DAT
  
          org   0              
  
  LCDgen        mov   dira,  outPins           'make outputs
  
                movi  vcfg,  #%0_01_0_0_0_000   'VCFG set to 8-bit, 2-color).               
                movd  vcfg,  #%000000_000       'pins 7..0 for video output
                movs  vcfg,  #%0_0101_0010    'mask to be used for video output -
                
                mov  VSCLset,  _VSCLset
                mov  vscl,  VSCLset          'mov timing of video output to vscl register
  
                mov   FREQa,  _FREQa
                mov   frqa,  FREQa             'set frequency of CTRA
                movi  ctra,  #%000001_101     'config counterA in video mode-divisor of ...4
  
                mov  FREQb, _FREQb
                mov  frqb,  FREQb             'set frequency of CTRb
                movs ctrb, 0_0000_0001        'set output pin from ctrb - p0
                movi ctrb, #%00100_111        'config CTRb NCO-single ended, div of 1
                
                mov  pixels,  _pixels  '
                mov  colors,  _colors
  
           
  :loop         waitvid  colors, pixels  
                  jmp  #:loop              
                
                                                        
  
  _pixels        long      %0101_0101_0101_0101_0101_0101_0101_0101    '0,1,0,1,0,1 etc          
  _colors        long      %1111_1111_1111_1111_1111_1111_0000_0000   ' 0=0's,  1=1's
  
  outpins        long      %0000_1000_0000_0000_0000_0000_1111_1111   '
  _VSCLset       long      %0000_0001_____0000_0010_0000              '
  _FREQa         long      $1000_0000  
  _FREQb         long      $1000_0000
  
  pixels        res       1
  colors        res       1
  VSCLset       res       1
  FREQa         res       1
  FREQb         res       1
  
  
• ericball Posts: 774

  2011-01-06 12:20 edited 2011-01-06 12:20

  homosapien wrote: »

  However, the output from the VGU is (with divider set to 1/4) 10MHz as Eric says. I would have expected 5MHz/4 =1.25MHz.

  
  The PLL takes the output of PHS[31] then multiplies this frequency by 16 which is then divided down by PLLDIV. This is all explained in "PLL modes of operation" in Application Note 001 Propeller Counters. The place which I usually get confused in with PLLDIV. Just remember the divide is to the VCO output which is 16x the input frequency (which must be between 4 & 8 MHz). So the output frequency is 16x - 1/8 the input frequency.
• homosapien Posts: 147

  2011-01-06 18:15 edited 2011-01-06 18:15

  OK, I found and read the App. Note 001 and this all makes a lot more sense. I will need some time to run some test code and hardware setups, but I think I have a handle on this now.
  
  Thanks for your help and pointing me in the right direction.
  
  -h