Connecting Prop to a ADC
SSkalko
Posts: 9
I am working on a program to connect the Prop to a ADC (ADS7818P-ND http://focus.ti.com/lit/ds/symlink/ads7818.pdf ) not much luck so far. I am wondering if I need to use pull-up or pull-down resistors on the DATA, Clock and Enable connections between the IC and the Prop. I have a feeling I make need to invest in something like the USB oscilloscope that Parallax sells to make some head way on this.
Comments
I use one counter to output a continuous clock signal, use waitpeq/waitpne instructions to sync the reads, test the data line, rotate the carry flag into my result register, and store the full result in hub memory. See the attachment for more info.
DAT org ADC mov dira,#$0000_0005 ' P0-Clk, P1-Data, P2-Conv mov frqa,CtrFreq mov ctra,CtrCfg mov ADC_Add,#@Hub_Memory_1 ' Store relative address add ADC_Add,PAR ' Add relative address to absolute address of ADC routine :reset mov ADC_Bit_Counter,#3 mov ADC_Data,#0 ' Clear ADC_Data register :reset_loop waitpne CLK_Mask,CLK_Mask ' Wait for clock to go low waitpeq CLK_Mask,CLK_Mask ' Wait for clock to go high djnz ADC_Bit_Counter,#:reset_loop ' Wait for three clocks andn outa,Conv_Mask ' Clear CONV to begin data transmit mov ADC_Bit_Counter,#13 ' Initialize to rotate 12 bits into ADC_Data :loop ' Number of instructions in loop determines maximum clock rate, loop takes a minimum of four instructions ' waitpne CLK_Mask,CLK_Mask ' This line only necessary for slow clocks (already low at 4MHz) waitpeq CLK_Mask,CLK_Mask ' Wait for clock to go high test Data_Mask,ina wc ' Test Data pin, set C if high rcl ADC_Data,#1 ' Rotate C into ADC_Data djnz ADC_Bit_Counter,#:loop ' Loop if 12 bits not rotated in or outa,Conv_Mask ' Raise CONV to begin sampling mode wrword ADC_Data,ADC_Add ' Store ADC_Data word at calculated absolute address of Hub_Memory_1 jmp #:reset '-------------------------------------------------------------------------- CtrCfg long %0_00100_000_00000000_000000_000_000000 ' NCO, P0 CtrFreq long 214_748_364 ' 4MHz CLK_Mask long $0000_0001 ' CLK on P0 Data_Mask long $0000_0002 ' Data on P1 Conv_Mask long $0000_0004 ' CONV on P2 ADC_Bit_Counter long 13 ' Count 13 clocks ADC_Data res 1 ' Working register for received data ADC_Add res 1 ' Address in hub memory to store valid dataMy saelig logic analyzer is money for this sorta stuff.