multiple prop D/A A/D question.
rjo_
Posts: 1,825
I am in the process of becoming the proud father of twin piggybacked props. So, I'm trying to line up a sequence of little projects I want to do... somewhere near the top of the list comes this:
There will always be a good safe maximum sampling rate for D/A applications and there will always be applications where that particular sampling rate just isn't enough.
The only thing that will ever change is exactly what that safe maximum sampling rate is.
What would stop us from using a 10Mhz clock external to two Props... and then simply switch the clock line between the two props every clock cycle? In effect, each prop would be getting a 5Mhz clock... put there would be a 1/2 clock cycle delay between them.
Then set up a perfectly identical D/A arrangement... right down to which cog and which pin is doing the work on each prop, split the signal line to each prop and do interleaved acquisition... When that was done... reorder the data. For that matter what would stop us from using a 100Mhz clock with 10 props to achieve a 10 fold increase in the maximum sampling rate?
Obviously, every time you double the number of props... you also double the amount of hub ram available. So, as you increase your sampling rate you are also increasing the total amount of hub ram... system wide.
On the signal synthesis side you would essentially reverse the process...not exactly but the first step would be to serially partition the data across the prop network
In theory, I don't see why it shouldn't work... but practical reality sometimes intervenes, and there may be a fact I'm not aware of that shoots the "theory" part to bits.
I'm not saying that this would work without some careful electronic design. I'm simply asking if anyone knows a serious issue that would tend to make it the equivalent of rocket science to get it to work.
Thanks.
Rich
There will always be a good safe maximum sampling rate for D/A applications and there will always be applications where that particular sampling rate just isn't enough.
The only thing that will ever change is exactly what that safe maximum sampling rate is.
What would stop us from using a 10Mhz clock external to two Props... and then simply switch the clock line between the two props every clock cycle? In effect, each prop would be getting a 5Mhz clock... put there would be a 1/2 clock cycle delay between them.
Then set up a perfectly identical D/A arrangement... right down to which cog and which pin is doing the work on each prop, split the signal line to each prop and do interleaved acquisition... When that was done... reorder the data. For that matter what would stop us from using a 100Mhz clock with 10 props to achieve a 10 fold increase in the maximum sampling rate?
Obviously, every time you double the number of props... you also double the amount of hub ram available. So, as you increase your sampling rate you are also increasing the total amount of hub ram... system wide.
On the signal synthesis side you would essentially reverse the process...not exactly but the first step would be to serially partition the data across the prop network
In theory, I don't see why it shouldn't work... but practical reality sometimes intervenes, and there may be a fact I'm not aware of that shoots the "theory" part to bits.
I'm not saying that this would work without some careful electronic design. I'm simply asking if anyone knows a serious issue that would tend to make it the equivalent of rocket science to get it to work.
Thanks.
Rich
Comments
If on the other hand you wanted to do something like have two camera arrays looking at the same thing you can double the overall frame rate by putting the shutters out phase, that might need two props out of phase too.
Graham
I'm just starting to noodle this... and I'm thinking that if we want to build a multiple prop set up... we are going to need a flexible clocking system...external to the prop architechture.
At this point, I was just looking at taking a single external signal and doing "gang" A/D on it to increase the sampling frequency. Just figuring out how to explain it so that Mike can understand my question is the first hurdle...But, Mike is pretty smart... and he "devined" the question properly. I am definitely not an engineer[noparse]:)[/noparse] But I figure, if I solve problems... one at a time... with a lot help, eventually...
Thanks,
Rich
Probably.
Graham