Counters for dummies (work in progress)
Graham Stabler
Posts: 2,507
I've started writing up what I have learnt about the counter modules in an effort to hammer home the ideas with myself and to give others an easier time of it.
I've not finished it but thought I'd post to check if what I have written is correct so far and if I'm heading in the right direction.
It is designed to accompany the manual rather than replace it, you need to have read or have available pages 204-207 the section covering CTRA/CTRB.
The next part to write is the stuff that Tracy went through so nicely in the other counter thread.
Graham
I've not finished it but thought I'd post to check if what I have written is correct so far and if I'm heading in the right direction.
It is designed to accompany the manual rather than replace it, you need to have read or have available pages 204-207 the section covering CTRA/CTRB.
The next part to write is the stuff that Tracy went through so nicely in the other counter thread.
Graham
Comments
Whilst I've not yet read it, I'm sure this is going to be ultra-useful to me. Thank you very much
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Cheers,
Simon
Graham
· First of all, a great start.
· I think a block diagram of the whole system would help. Something like:
· FRQx -> PHSx -> PLL -> Divider -> Pin
· Of course there would be lines to show if the PLL is bypassed, etc.
Bean.
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Graham
Context would be useful. Something quite simple to build
I haven't really seen the need to use the SXes Capture and Compare feature because I have no idea of what applications I might want them for.
Similarly, the counter's in the Propeller are a bit too much for me as I have yet to really take on video signals. I have really been waiting for Andre LaMothe to provide a text that will fill the void.
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For purposes of clarity, I suggeest the diagram should tackle one mode at a time. For example, at the top of the table of modes, there is nothing conditional. It is either "never" or "always", so a diagram for those modes can leave out the conditional logic. And for the first diagram, for the NCO and DUTY modes, the PLL can be omitted. Incllude it for the next section of the tutorial. That leaves a much simpler and more comprehensible diagram for the "dummy", uhhh, beginner. The diagram for DUTY will also need the possibility of attaching the output pin(s) to the carry bit of PHS.
BTW, the PLL dividers only do divide by up to 16, not 32, 64, 128.
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Tracy Allen
www.emesystems.com
Tracy,
Although I have used the term for dummies it wasn't my intention to catalogue every single mode of operation in full detail, the manual does that. My hope is to just explain how they work and how they might be used and fill the gaps.
Although seperate diagrams might be clearer they would need a much more long winded description that I think actually complicates matters, you don't need to remember every single mode all you need is the basic idea of how it works and an understanding of how to read the mode table. I like the idea of considering the possible path of FRQx on its route to the pins. I'll see how the document pans out, I'm not ruling it out. Good point on the carry bit!!
On the PLL division, the manual (table 4-6) shows divisions from 1 to 128. It also states that it is the VCO that is divided. So at least according to the description and the table it is multplied by 16 and then divided by a power of two. But doesn't that make the maximum division 8??? I suspect that the manual is failing to really explain what it means by division, it already assumes a working knowledge of a PLL. You seem to have some extra info (via Chip?) can you explain further?
Cheers,
Graham
In mode 00001, where does the output of the PLL go? Can the divide still be used?
Graham
Re the division ratio, you are absolutely correct. My bad, I was thinking about something else. The PLLDIV has 3 bits that give division ratios of 128,64,...,2,1 as you have in your diagram. If the input to the PLL is restricted to the range of 4 to 8 mhz, outputs from the divider chain can cover the range of 500 khz to 128 mhz.
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Tracy Allen
www.emesystems.com
Recently I wanted to make a DAC, following one of the published assembly examples where a delta-sigma ADC fed values to a DAC, except I wanted a simple standalone DAC that would accept input values and emit a voltage.
I was able to get a circuit working, but it was tough. The only documentation I could find was pages 204-207 of the latest manual, but that doesn't really explain much of anything at a beginner level. I still don't really understand how my circuit works, although I can feed it values and it emits a smooth output from 2.2 mv all the way up to 3.28 volts, so it seems to be doing exactly what I wanted.
Some simple explanations, maybe with some simple example external circuits and complete example code, would be very useful.
David
I understand calls for examples but in some cases I get the feeling that is really a call to be able to use a feature without having to understand it. The counters aren't so difficult really you just need some confidence and a few minutes to sit down and read my documentation (when its finished and assuming its any good).
What I might do it produce some counter based objects such as a PWM, ADC, DAC etc using the published examples but I'll comment them to the max.
Graham
I read your PDF last night and am pleased to report that the subject's a whole lot less fuzzy to me now
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Cheers,
Simon
Thanks Graham,
Martin
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Martin Hebel
Southern Illinois University Carbondale - Electronic Systems Technologies
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Since the counter PLLs are different from the system clock PLL -- For minimum confusion and reduced bugs, different constant names should be used instead of PLL16X (Maybe PLLDIV_1 to PLLDIV_128 ?).
Your diagram should then show the PLLDIV box on the side as a register control instead of in-line in the bitstream.
Graham
Graham
When I started with the propeller there wasn't much of any documentation anywhere on counters.
So I'm glad to see things like this in the works.
I have called the boxt PLL X16 because the box is a PLL that multiplies by 16 I'm not refering to a register. I make the divide a box on its own to show the process of division, the signal is multiplied by 16 and then divided in affect. The box contains a * showing that the division is controlled by the CTR register, it is not designed to represent the register PLLDIV.
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Oops, I realized this is what you intended·after the fact. In your diagram, PLLDIV controls the selector switch.
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