SX/B compiler crash

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' =========================================================================
'
'   Started... 01-Mar-2005
'   Updated...
'
' =========================================================================

' -------------------------------------------------------------------------
' Program Description
' -------------------------------------------------------------------------

' -------------------------------------------------------------------------
' Device Settings
' -------------------------------------------------------------------------
DEVICE          SX28, OSCHS3, TURBO, STACKX, OPTIONX
  IRC_CAL IRC_FAST
FREQ            25_000_000

' -------------------------------------------------------------------------
' IO Pins
' -------------------------------------------------------------------------

' -------------------------------------------------------------------------
' Constants
' -------------------------------------------------------------------------
'int_period CON 166  ; This sets the I2C bus frequency.  (50MHz chip and 100kHz bus)
'int_period CON 108  ; This sets the I2C bus frequency.  (50MHz chip and 154kHz bus)
int_period CON 83  ; This sets the I2C bus frequency.  (25MHz chip and 100kHz bus)
     '; Also used as seed for UART baud rate.
     '; int_period = clk_speed/(3 x bus_speed)
      '; eg. for 100kHz operation : int_period = 50Mhz/(3 x 100kHz) = 166

strt_delay CON 4 'How long (in clock cycles) to wait for start bit (or something)

 ';*********************************************************************************
 '; UART Constants
 '; The following three values determine the UART baud rate.
 '; The value of baud_rate and int_period affect the baud rate as follows:
 ';  Baud rate = 50MHz/(baud_rate * int_period * RTCC_prescaler)
 ';  Baud rate = 25MHz/(12? * 83 * ??? )
 '; 12? * ??? = (19200 * 83 )/25MHz
 '; 12? * ??? = (19200 * 166 )/50MHz
 ';
 '; Note: *int_period must <256 and longer than the length of the slowest possible
 '; interrupt sequence in instruction cycles. Changing the value of int_period will
 '; affect the rest of the virtual peripherals due to timing issues. The start delay
 '; value must be set equal to (baud_rate)*1.5 + 1
 ';*********************************************************************************
'; *** 2400 baud (for slower baud rates, increase the RTCC prescaler)
baud_rate_24 CON 96   ';for 2400 baud rate generation
start_del_24 CON baud_rate_24+(baud_rate_24/2)+1
'; *** 9600 baud
baud_rate_96 CON 24   ';for 9600 baud rate generation
start_delay_96 CON  baud_rate_96+(baud_rate_96/2)+1
'; *** 19200 baud
baud_rate_192 CON 12   ';for 19200 baud rate generation
start_delay_192 CON  baud_rate_192+(baud_rate_192/2)+1
'; *** 38400 baud
baud_rate_384 CON 6   ';for 38400 baud rate generation
start_delay_384 CON  baud_rate_384+(baud_rate_384/2)+1
'; *** 57600 baud
baud_rate_576 CON 4   ';for 57600 baud rate generation
start_delay_576 CON baud_rate_576+(baud_rate_576/2)+1
';*****************************************************************************************
'; Port Assignment
';   RX_io  : sets direction registers
';   RX_init : sets the ports initial value
';*****************************************************************************************
RA_init  CON %11111111  ';SX18/20/28/48/52 port A latch init
RA_io  CON %11111111  ';SX18/20/28/48/52 port A DDIR value
RB_init  CON %11111111  ';SX18/20/28/48/52 port B latch init
RB_io  CON %01110111  ';SX18/20/28/48/52 port B DDIR value
RC_init  CON %00011111  ';SX18/20/28/48/52 port C latch init
RC_io  CON %00011100  ';SX18/20/28/48/52 port C DDIR value
 
 
';*****************************************************************************************
'; Pin Definitions 
';*****************************************************************************************
i2c_port VAR rb
uart_port VAR ra
led_port VAR rc
scl  CON 1
sda  CON 0
scl_pin        VAR     i2c_port.scl '; I2C clock
sda_pin        VAR     i2c_port.sda '; I2C data I/O
rx_pin1         VAR     uart_port.2 ;UART1 receive input
tx_pin1         VAR     uart_port.3 ;UART1 transmit output
rx_pin2         VAR     uart_port.6 ;UART2 receive input
tx_pin2         VAR     uart_port.7 ;UART2 transmit output

';Address of the slave device
MWSlave  CON $88
'; Optional LEDs for debugging purposes...
green_led VAR led_port.7 
red_led2 VAR led_port.6
red_led1 VAR led_port.5

'';*****************************************************************************************
'; Data Memory address definitions
'; These definitions ensure the proper address is used for banks 0 - 7 for 2K SX devices
'; (SX18/20/28) and 4K SX devices (SX48/52). 
';*****************************************************************************************
global_org CON $08
bank0_org CON $10
bank1_org CON $30
bank2_org CON $50
bank3_org CON $70
bank4_org CON $90
bank5_org CON $B0
bank6_org CON $D0
bank7_org CON $F0
' -------------------------------------------------------------------------
' Variables
' -------------------------------------------------------------------------
 
main_temp VAR Byte
isr_temp VAR Byte  ; Temporary variable used by the ISR.
flags  VAR Byte
 uart_rx_flag  VAR flags.0  ; flag set when data received by UART
 active_uart_isr_flag  VAR flags.1  ; uart flag used in ISR to switch between UARTs
main_temp2 VAR Byte
main_temp3 VAR Byte
main_temp4 VAR Byte
MyCount  VAR Byte

ISrSlice VAR Byte
I2CWorkSet VAR Byte(8)
 I2C_State VAR I2CWorkSet(0)
 I2C_Sub_State VAR I2CWorkSet(1)
 I2C_Strt_Ctr VAR I2CWorkSet(2)
 I2C_Index VAR I2CWorkSet(3)
 I2C_Byte VAR I2CWorkSet(4)
 I2C_Bit_Count VAR I2CWorkSet(5)
 I2C_Num_bytes VAR I2CWorkSet(6)
 I2C_Flags VAR I2CWorkSet(7)
  I2C_nack VAR I2C_flags.0 '; This bit is set if the I2C master has received a NACK from the slave
  I2C_rx_flag VAR I2C_flags.1  '; Indicates that the number of bytes requested have been received
  I2C_lost_arb VAR I2C_flags.2 '; indicates that this master has lost arbitration
  I2C_doing_write VAR I2C_flags.4 '; Used to remember whether doing a read or write when recovering from loss of arbitration
  I2C_in_control VAR I2C_flags.5 '; Indicates that this master thinks it is in control of the I2C bus
  I2C_Busy VAR I2C_flags.6 '; Indicates that this master thinks it is in control of the I2C bus
    I2C_buffer VAR Byte(6) '$ ; The buffer uses the last 7 registers of this bank (pre-increments, so put I2CM buffer here.)
 I2C_address VAR I2C_Buffer(0) '; The address to read/write to.
 I2C_data_0  VAR I2C_Buffer(1) '; Data buffer 
 I2C_data_1 VAR I2C_Buffer(2) '; Data buffer
 I2C_data_2 VAR I2C_Buffer(3) '; Data buffer
 I2C_data_3 VAR I2C_Buffer(4) '; Data buffer
 I2C_data_4 VAR I2C_Buffer(5) '; Data buffer
' I2C_data_5 VAR I2C_Buffer(6) '; Data buffer
I2CaVars VAR Byte(8)  'Reserves the space for the moment
 I2Ca_State VAR I2CaVars(0)
 I2Ca_Sub_State VAR I2CaVars(1)
 I2Ca_Strt_Ctr VAR I2CaVars(2)
 I2Ca_Index VAR I2CaVars(3)
 I2Ca_Byte VAR I2CaVars(4)
 I2Ca_Bit_Count VAR I2CaVars(5)
 I2Ca_Num_bytes VAR I2CaVars(6)
 I2Ca_Flags VAR I2CaVars(7)
  I2Ca_nack VAR I2Ca_flags.0 '; This bit is set if the I2C master has received a NACK from the slave
  I2Ca_rx_flag VAR I2Ca_flags.1  '; Indicates that the number of bytes requested have been received
  I2Ca_lost_arb VAR I2Ca_flags.2 '; indicates that this master has lost arbitration
  I2Ca_doing_write VAR I2Ca_flags.4 '; Used to remember whether doing a read or write when recovering from loss of arbitration
  I2Ca_in_control VAR I2Ca_flags.5 '; Indicates that this master thinks it is in control of the I2C bus
  I2Ca_Busy VAR I2Ca_flags.6 '; Indicates that this master thinks it is in control of the I2C bus
    I2Ca_Buffer VAR Byte(6) '$ ; The buffer uses the last 7 registers of this bank (pre-increments, so put I2CM buffer here.)
 I2Ca_address VAR I2Ca_Buffer(0) '; The address to read/write to.
 I2Ca_data_0  VAR I2Ca_Buffer(1) '; Data buffer 
 I2Ca_data_1 VAR I2Ca_Buffer(2) '; Data buffer
 I2Ca_data_2 VAR I2Ca_Buffer(3) '; Data buffer
 I2Ca_data_3 VAR I2Ca_Buffer(4) '; Data buffer
 I2Ca_data_4 VAR I2Ca_Buffer(5) '; Data buffer
' I2Ca_data_5 VAR I2Ca_Buffer(6) '; Data buffer

I2CbVars VAR Byte(8)  'Reserves the space for the moment
 I2Cb_State VAR I2CbVars(0)
 I2Cb_Sub_State VAR I2CbVars(1)
 I2Cb_Strt_Ctr VAR I2CbVars(2)
 I2Cb_Index VAR I2CbVars(3)
 I2Cb_Byte VAR I2CbVars(4)
 I2Cb_Bit_Count VAR I2CbVars(5)
 I2Cb_Num_bytes VAR I2CbVars(6)
 I2Cb_Flags VAR I2CWorkSet(7)
  I2Cb_nack VAR I2Cb_flags.0 '; This bit is set if the I2C master has received a NACK from the slave
  I2Cb_rx_flag VAR I2Cb_flags.1  '; Indicates that the number of bytes requested have been received
  I2Cb_lost_arb VAR I2Cb_flags.2 '; indicates that this master has lost arbitration
  I2Cb_doing_write VAR I2Cb_flags.4 '; Used to remember whether doing a read or write when recovering from loss of arbitration
  I2Cb_in_control VAR I2Cb_flags.5 '; Indicates that this master thinks it is in control of the I2C bus
  I2Cb_Busy VAR I2Cb_flags.6 '; Indicates that this master thinks it is in control of the I2C bus
    I2Cb_buffer VAR Byte(6) '$ ; The buffer uses the last 7 registers of this bank (pre-increments, so put I2CM buffer here.)
 I2Cb_address VAR I2Cb_Buffer(0) '; The address to read/write to.
 I2Cb_data_0  VAR I2Cb_Buffer(1) '; Data buffer 
 I2Cb_data_1 VAR I2Cb_Buffer(2) '; Data buffer
 I2Cb_data_2 VAR I2Cb_Buffer(3) '; Data buffer
 I2Cb_data_3 VAR I2Cb_Buffer(4) '; Data buffer
 I2Cb_data_4 VAR I2Cb_Buffer(5) '; Data buffer
' I2Cb_data_5 VAR I2Cb_Buffer(6) '; Data buffer
 
';*****************************************************************************************
'; Global Register definitions
'; NOTE: Global data memory starts at $0A on SX48/52 and $08 on SX18/20/28.
';*****************************************************************************************
  '???  org     global_org

' -------------------------------------------------------------------------
  INTERRUPT
' -------------------------------------------------------------------------
SWFlags  VAR byte
WhichI2C VAR SWFlags.0
PBuf  VAR Byte(2)
Param_Ptr VAR byte
ISR_Start:
  ' ISR code here
 'ALWAYS perform ISR handling for I2C busses - one on each cycle
     'Perform I2C handling - 1 and 2
 if WhichI2C = 0 goto ISRI2Cb
ISRI2Ca:
 'Perform I2Ca handling
 GOSUB I2C_ISR, @I2CaVars(0)
 GOTO ToggI2C
ISRI2Cb:
 'Perform I2Cb handling
 GOSUB I2C_ISR, @I2CbVars(0) 'or a long list of them
ToggI2C: 'Toggle between I2C busses for the next ISR cycle.
 WhichI2C=NOT WhichI2C
     'Start of ISR for I2C
I2C_ISR:
 'Get the variables (Parameters???? related to the calling instance
 Param_Ptr = __PARAM1
 GET Param_Ptr, I2C_State, I2C_sub_state, I2C_Strt_Ctr, I2C_Index, I2C_Byte, I2C_Bit_Count, I2C_Num_bytes
 'Now operate the State machine for I2C bus
 BRANCH I2C_State, I2C_idle, I2C_Start, I2C_start_write, I2C_write, I2C_write, I2C_get_ack, I2C_write_repeat, I2C_stop, I2C_start, I2C_start_read, I2C_write, I2C_get_ack, I2C_read_data, I2C_read, I2C_store_byte, I2C_send_ack, I2C_stop
     'State routines
' ;*********************************************************************************'
' ; State: I2CM_idle
' ;  This is the state that the I2C Master is usually in when it is not in use.
' ;  It just ensures that the I2C_port_buf SCL and SDA are both set high
' ;*********************************************************************************
I2C_idle:  'Main State - idle
 \ setb I2C_port_buf.sda 
 \ setb I2C_port_buf.scl 
 goto State_Done
' ;*********************************************************************************
' ; State: I2CM_start
' ;  When any mainline program wants to use the I2C master it puts the master into
' ;  start mode.  This mode creates a start condition on the I2C bus.  A start 
' ; condition is created when SDA goes from high to low while SCL stays high.
' ;*********************************************************************************
I2C_start:  'Main State for starting
 BRANCH I2C_sub_state, SubState1, SubState2, SubState3, SubState4, Substate5
SubState1:
  \ setb I2C_port_buf.scl ;1
 \ setb I2C_in_control  ;1
 \ setb I2C_port_buf.sda ;1
 I2C_strt_ctr = strt_delay 'Set start delay using a constant  ;2
 goto IncSubState
SubState2:   '; --- WAITING FOR STOP/START OR IDLE SCL ---
 \ sb scl_pin   ';1 
 \ clr I2C_sub_state  ';1 
 DEC I2C_strt_ctr  ';1/2
 IF Z = 0 GOTO State_Done '   ;3
 goto IncSubState  '  ;3 = 6/8 + 7 = 13/15
SubState3:  'Finished Clock synchronisation (I think)
 \ clrb I2C_port_buf.sda ';1
 goto IncSubState  '  ;3 = 5 + 7 = 12
SubState4:
 \ clrb I2C_port_buf.scl ';1
 goto IncSubState  '  ;3 = 6/8 + 7 = 13/15
SubState5:
 \ setb I2C_port_buf.sda ;1
 \ clr I2C_sub_state  ;1
 'goto IncSubState    ;3 = 6/8 + 7 = 13/15
IncSubState:
 INC I2C_sub_state
 Goto State_Done

' ;*********************************************************************************
' ; State: I2CM_start_write 
' ; This state performs some pre-processing which allows the I2CM_write state to
' ; do its work.  It sets up the bit count, gets the next piece of data from the
' ; buffer and prepares to send it.
' ;*********************************************************************************
I2C_start_write:   'Main State start a write cycle
 INC  I2C_index
 GET I2C_Index, I2C_Byte 'Get the byte pointed at by the index ptr.
    'What is full address - ASM code ???
 I2C_Bit_Count = 8 '8 bits to send.
 INC  I2C_State 'go to the next state
 GOTO State_Done
'  inc I2CM_index  ';1'
'  mov w,I2CM_index  ';1
'  add fsr,w   ';1
'  mov w,indf   ;1
'  mov I2CM_byte,w  ;1
'  mov w,#8   ;1
'  mov I2CM_bit_count,w ;1
'  inc I2CM_state  ;1
 
'  retp    ;3 = 12 + 7 = 19
' ;*********************************************************************************'
' ; State: I2CM_write
' ; This state writes the data in I2CM_byte to the I2C bus
' ;*********************************************************************************
I2C_write:   'Main State - do writing 
 BRANCH I2C_sub_state, wstate1, wstate2, wstate3 
wstate1:
 \ setb I2C_in_control
 \ setb I2C_port_buf.sda ;1
 \ rl I2C_byte  ;1
 \ sc    ;1
 \ clrb I2C_port_buf.sda ;1
 INC I2C_sub_state  ';1
 goto State_Done         'retp    ;3 = 15 + 7 = 22
wstate2:
 \ setb I2C_port_buf.scl ;1
 INC I2C_sub_state  ';1
 goto State_Done  'retp    ;3 = 12 + 7 = 19
wstate3:
 \ clrb I2C_port_buf.scl ;1
 DEC I2C_bit_count  ';1
 'snz    ;1
 IF I2C_bit_count = 0 GOTO Wdone
 'jmp :done   ;3
 I2C_sub_state = 0 'clr I2CM_sub_state  ;1
 goto State_Done  'retp    ;3 = 14 + 7 = 21
Wdone:
 I2C_sub_state = 0  ';1
 INC I2C_state  ';1
 \ clrb I2C_in_control
 goto State_Done

' ;*********************************************************************************
' ; State: I2CM_get_ack
' ; This state gets an ACK from the slave device.  If no ACK is received, the I2C
' ; Master state machine puts a stop condition on the bus and the I2CM_flags 
' ; register is loaded to indicate that a NACK has occurred.
' ;*********************************************************************************
I2C_get_ack:
  BRANCH I2C_Sub_State, GetAckState1, GetAckState2, GetAckState3, GetAckState4
'  mov w,I2CM_sub_state ;1'
'  add pc,w   ;3
'  jmp :state1   ;3
'  jmp :state2   ;3
'  jmp :state3   ;3
'  jmp :state4   ;3
':state1
GetAckState1:
 \ setb I2C_port_buf.sda ';1
 INC I2C_sub_state  ';1
 GOTO State_Done 'retp    ;3 = 13 + 7 = 20
':state2
GetAckState2:
 \ setb I2C_port_buf.scl ';1
GetAckStateDone:
 INC I2C_sub_state  ';1
 GOTO State_Done 'retp    ;3 = 12 + 7 = 19
':state3
GetAckState3:
 if sda_pin = 0 GOTO State3done
' sb sda_pin   ;1
' INC I2C_sub_state  ';1
' sb sda_pin   ;1
 LET I2C_State = 20 'I2C_Stop_Loc - I2C_Idle_Loc  'Set the value of the STOP state.
'  mov w,#(I2CM_stop_loc-I2CM_idle_loc);1
'  mov I2CM_state,w  ;1
 \ clr I2C_sub_state  ;1 ;send a stop and indicate that this didn't work.
 \ setb I2C_NACK  ;1 ;set I2CM_NACK to show that this did not go through.
 GOTO State_Done  'retp    ;3 = 17 + 7 = 24
':state4
GetAckState4:
 \ clrb I2C_port_buf.scl ;1
 \ clr I2C_sub_state  ;1
 INC I2C_state  ';1 ;move on to next state
 GOTO State_Done  'retp    ;3 = 13 + 7 = 20

' ;*********************************************************************************
' ; State: I2CM_write_repeat
' ; This state determines, after one byte of data is sent, whether or not
' ;  there is another byte to be sent.  If so, this state goes back to 
' ; I2CM_start_write and sends the next byte.
' ;*********************************************************************************
I2C_write_repeat:
 if I2C_num_bytes = I2C_index GOTO I2C_Write_Done
'  mov w,I2CM_num_bytes ;1 ;test the read index to see if it is = to write index.'
'  xor w,I2CM_index  ;1 ;if it is, then we have finished writing the buffer via. I2C.
'  snz    ;1
'  jmp :I2CM_write_done ;3
 I2C_State = I2C_State - 3 'Step the state back to Write data
'  dec I2CM_state  ;1 ;back to get_ack
'  dec I2CM_state  ;1 ;back to write
'  dec I2CM_state  ;1 ;back to write_data
 GOTO State_Done  'retp    ;3 = 16 + 7 =23
I2C_write_done:
 INC I2C_state  ';1 ;move on to next state (stop)
 GOTO State_Done 'retp    ;3 = 17 + 7 = 24;and start the stop bit 
' ;*********************************************************************************
' ; State: I2CM_stop
' ; This state puts a stop condition on the I2C bus and resets the state machine back
' ; to its idle state.  A stop condition is when SDA goes from low to high while SCL
' ; is high.
' ;*********************************************************************************
I2C_stop:
 BRANCH I2C_Sub_State, StopSubState1, StopSubState2, StopSubState3
'  mov w,I2CM_sub_state ;1
'  add pc,w   ;3
'  jmp :state1   ;3
'  jmp :state2   ;3
'  jmp :state3   ;3
StopSubState1:
 \ setb I2C_in_control
 \ clrb I2C_port_buf.sda ;1
 \ inc I2C_sub_state  ;1
 GOTO  State_Done  'retp    ;3 = 13 + 7 = 20
StopSubState2:
 \ setb I2C_port_buf.scl ;1
 \ inc I2C_sub_state  ;1
 GOTO State_Done 'retp    ;3 = 13 + 7 = 20
StopSubState2:
 \ setb I2C_port_buf.sda ;1
 \ clr I2C_sub_state  ;1 ;put the state machine in Idle
 \ clr I2C_state  ;1
 \ clr I2C_num_bytes  ;1
 I2C_Index = $FF
'  mov w,#$ff   ;1
'  mov I2CM_index,w  ;1
 \ clrb I2C_in_control
 GOTO State_Done  'retp    ;3 = 16 + 7 = 23 
 
' State Done is where we exit the routine.
' it does not mean that we have finished with a state - only that this cycle of it has completed
State_Done:
 'Pass the parameters for this instance back to the caller locations
 PUT Param_Ptr, I2C_State, I2C_sub_state, I2C_Strt_Ctr, I2C_Index, I2C_Byte, I2C_Bit_Count, I2C_Num_bytes
 RETURN
 'End of the I"C state machine
'*****************************
'End of I2C part of ISR handling
' Move on to servicing the other routines.
'*****************************

'How do we get here????????????????????????????????
 'Decrement the ISR counter
 DEC ISRslice
PickISR:
 BRANCH ISRslice, Slice0, Slice1, Slice2, Slice3, Slice4, Slice5, Slice6, Slice7, Slice8, Slice9
Slice0:
 ISRslice = 2  'There are 'n' interrupt slices
 'Zero is a non-runner - go to num '5'
 goto PickISR
Slice1: 'Count until ok to do some RS232a
 GOTO EndSlice
Slice2: 'Count until ok to do some RS232b
 GOTO EndSlice
Slice3:
 ISRslice = 5  'There are 'n' interrupt slices 
 GOTO EndSlice
Slice4:
 ISRslice = 5  'There are 'n' interrupt slices
 GOTO EndSlice
Slice5:
 ISRslice = 5  'There are 'n' interrupt slices
 GOTO EndSlice
Slice6:
 ISRslice=5  'There are 'n' interrupt slices
 GOTO EndSlice
Slice7:
 ISRslice=5  'There are 'n' interrupt slices
 GOTO EndSlice
Slice8:
 ISRslice=5  'There are 'n' interrupt slices
 GOTO EndSlice
Slice9:
 ISRslice=5  'There are 'n' interrupt slices
 GOTO EndSlice
EndSlice:
ISR_Exit:
 RETURNINT ' {cycles}                                 

' =========================================================================
  PROGRAM Start
' =========================================================================
Pgm_ID:
  DATA  "XLights", 0

' -------------------------------------------------------------------------
' Subroutines / Jump Table
' -------------------------------------------------------------------------
I2CaSend:
 'Take "I2CaBytes" of data from "I2CaData" and send it to  "I2CaDevice & I2CaAddr".
 'First we wait for the bus to be not busy.
 IF I2Ca_Busy = 1 GOTO I2CaRcv    'NOT SURE IF THIS TEST IS RIGHT
 'Once we have the bus, then load the ISR and trigger the fetch
' GOBSUB xxx
 RETURN
I2CaRcv:
 'Read "I2CaBytes" of data from "I2CaDevice & I2CaAddr" and put it into "I2CaData"
 'First we wait for the bus to be not busy.
 IF I2Ca_Busy = 1 GOTO I2CaRcv
 'Once we have the bus, then load the ISR and trigger the fetch
 RETURN
 
I2CbSend:
 RETURN

I2CbRcv:
 RETURN
 
RS232aSend:
 RETURN

RS232aRcv:
 RETURN
 
RS232bSend:
 RETURN

RS232bRcv:
 RETURN
 
' -------------------------------------------------------------------------
' Program Code
' -------------------------------------------------------------------------
Start:
  ' initialization code here
 ISRSlice = 0  'Initialise interrupt counter
 'Set up the data ports for all the 
 RA = RA_init   'Set up Data ports
 TRIS_A = RA_io                            ' make LED ports outputs
 RB = RB_init   'Set up Data ports
 TRIS_B = RB_io                            ' make LED ports outputs
 RC = RC_init   'Set up Data ports
 TRIS_C = RC_io
 'Start up the interrupt handler.
Main:
  ' main code here
 pause 50
 GOSUB RS232bSend
 GOSUB I2CaSend
  GOTO Main 'Loop - to detect boundary failures.
 
' -------------------------------------------------------------------------
' Page 1 Code
' -------------------------------------------------------------------------
Page_1:
  ADDRESS $200
P1_Start:
  GOTO P1_Start                                 ' error if Pg0 overruns Pg1

' -------------------------------------------------------------------------
' Page 2 Code
' -------------------------------------------------------------------------
Page_2:
  ADDRESS $400
P2_Start:
  GOTO P2_Start                                 ' error if Pg1 overruns Pg2
 
' -------------------------------------------------------------------------
' Page 3 Code
' -------------------------------------------------------------------------
Page_3:
  ADDRESS $600
P3_Start:
  GOTO P3_Start                                 ' error if Pg2 overruns Pg3

 
'END

XML Dump info capture by microsoft  - best viewed in explorer I reckon.
 
 
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