Explanation of retiw please
Catware
Posts: 14
Hello guys,
I'm trying to figure out how to correctly set the offset for retiw. I've read the manual, beg program guide, and searched this site and sxlist and can't quite figure out how to correctly do so.
I am designing a frequency counter (for frequencies <500Hz). The program counts inbetween clock pulses, and when a new pulse comes in, it updates the display. Here's some sample code:
Can anyone explain how the offset for retiw should be set in this example?
Thanks,
David
Post Edited (Catware) : 2/1/2005 4:01:22 PM GMT
I'm trying to figure out how to correctly set the offset for retiw. I've read the manual, beg program guide, and searched this site and sxlist and can't quite figure out how to correctly do so.
I am designing a frequency counter (for frequencies <500Hz). The program counts inbetween clock pulses, and when a new pulse comes in, it updates the display. Here's some sample code:
org 0 ; code start
isr inc counter
snz
inc counter+1
mov !rb,#%00000000 ;read pending and clear
mov edges,w
jnb edges.0,:return ;no incoming edge->return
setb settings.0 ; clock pulse came in
mov lastcounter+1,counter+1
mov lastcounter,counter
clr counter
clr counter+1
:return mov w,#-256 ;interrupt every 20.48 uS (1000 instructions * 20ns per instruc / 4 prescaler)
retiw
start_point
[noparse][[/noparse]clear all variables]
mov !option,#%00000001 ;set RTCC to internal clock 1:4 ratio (20.48us)
mode $0D ;Logic Level Mode
mov !rb,#%00000001 ;one pin TTL
mode $0E ; pull up resistors
mov !rb,#%00000000 ; 8 pull ups
mode $0A ;Edge Detection
mov !rb,#%00000000 ;rising edge
mode $0F ;Direction Mode
mov !rb,#%11111111 ; 8 inputs
mov rb,#00 ;clear
mode $09 ;Enable Pending Register
main
jnb settings.0,:no_pulse
[noparse][[/noparse]compute 1/lastcounter * calibration to obtain Hz]
clrb settings.0
:no_pulse
call multiplexLEDs
jmp main
Can anyone explain how the offset for retiw should be set in this example?
Thanks,
David
Post Edited (Catware) : 2/1/2005 4:01:22 PM GMT
Comments
If so, the slowest interrupt period you can have is 50000000/256(prescaler)/256(rtcc overflow) = 762.939453125 or 1.31072 milliseconds.
Bean.
Post Edited (Bean) : 2/1/2005 7:48:57 PM GMT
I am using a 50Mhz clock, and do know how to set the prescaler. If I'm okay with interrupts occuring at the rtcc rollover rate (20.48us with 1:4 prescaler), then I don't need to mess with retiw? But if I wanted interrupts at 20.00us then I would set the retiw at #-250?
Hmmm, maybe that's the answer. I thought retiw was supposed to compensate for varying code execution times in the isr routine, but is its use only if you want different interrupt times than what the prescaler can give you?
p.s. it's 1.31ms, not 1.31usec· ·
If you want 256 you don't need retiw because RTCC keeps updating while in the interrupt routine, so the interrupt routines time is taken into account.
Bean.