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P2 Core Module — Parallax Forums

P2 Core Module

RaymanRayman Posts: 16,113
edited 2026-03-03 18:18 in Propeller 2

As part of a revised PLC type device, planning on using something tentatively called the "P2 Core Module". This is a 1.6" square with just the P2, bypass caps, and local regulators for VIO (one for each group of 8 P2 I/O pins).

So, there's not much to it, but it should allow easy access to high speed P2 on a regular 2-layer PCB.
So, could be good economically...

Should be able to be attached to main board either by either 0.05" headers (20 pins to a side), or directly soldered to PCB.

In any case probably want a cut out under the P2 for thermal reasons (if overclocking a lot).
Also, sometimes solder does weep through under the P2 and make a bump on the back side, so cut out maybe necessary if soldering directly to pcb...

Comments

  • RaymanRayman Posts: 16,113
    edited 2026-03-03 18:18

    I'm suddenly a big fan of OshPark for PCBs. Think going to order this thing today...

    Really like that it can directly accept Eagle PCB files and figure everything out.
    This is the first web thing that actually works fully with my Eagle pcb designs...

    Plus, price and speed are great.
    Purple is the only problem...

    1577 x 1420 - 542K
  • Interesting idea - it's basically a P2 breakout board, right?

    As for OSH Park, I like the purple. :wink:

    Paul

  • MicksterMickster Posts: 2,907
    edited 2026-03-07 16:00

    It appears that if you pre-order the P2, JLCPCB can deliver an assembled unit.

    Some nicer color options, also

    Link didn't work from here for some reason.
    https://jlcpcb.com/parts/componentSearch?searchTxt=Parallax

    It works when I use the JLCPCB "parts finder"

  • RaymanRayman Posts: 16,113

    @doggiedoc Guess that is right...

    The basic idea is that high speed and low noise P2 needs at least a 4 layer board. This can be a challenge to layout and expensive to prototype.
    This saves a step, you can just mount this on a 2 layer PCB and be done.
    Doing the larger main board in 4 or 6 or 8 layers would also cost a lot more and take longer to get made...

    The other thing for me, is that there are piles of prototype P2 boards here that have a P2 staring at me that I can't really recover.
    Well, I can recover with heat gun, but it takes forever and am not sure would completely trust the chip after that...
    This lets me just pop off the P2 and put on the next prototype.

  • RaymanRayman Posts: 16,113

    Here's the first design that uses the P2 Core. It is a revised version of P2 PLC in DMB-4773 case. This will be the middle board.
    In the middle of laying it out now. This is a 2-layer board that has some significant layout challenges, but think past that now.

    Anyway, odds are that this first version is not going to 100% perfect and I'll have to do a revision.
    In that case, just pop off the P2 Core and put in the next. Saving P2's from the trash!

    BTW: Doing the same thing with a $20 modular connector that would normally be soldered to this board. Tired of wasting those, so making it as a separate module as well.

    940 x 581 - 139K
  • RaymanRayman Posts: 16,113

    One design decision that might be questioning is not bringing out the 3.3V VIO...
    This module has 3.65 VDC (regulated to 3.3 VDC for VIO) and 1.8 VDC (for core, may be boosted for overclocking) as inputs.
    There is no 3.3 VDC output.

    But, I'm copying the P2 Eval headers here in 6 places that needs 3.3 VDC.
    Not really an issue, just dropping in a small 3.3 VDC regulator, fed by VIO, to get the 3.3 VDC for the headers.
    Something new, but not expecting any trouble...

  • RaymanRayman Posts: 16,113

    Putting a large cutout under the P2 in the above layout to aid in airflow for thermal reasons.

    But, you probably don't really need this unless overclocking.
    Not having it would allow one to put many components under the P2 Core module to save board space...

  • RaymanRayman Posts: 16,113

    Think could have added some optional PSRAM footprints to the bottom layer... Something to think about...

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