Wiznet W6300
ke4pjw
Posts: 1,240
in Propeller 2
Looks like Wiznet just dropped the W6300.
https://docs.wiznet.io/Product/iEthernet/W6300/overview
I hope this solves one of the problems that I found with the W6100. That is that UDP, when drinking from the firehose, would overrun the buffer. You literally could not get data out of the chip fast enough to keep up with the type of data needed for my light controller project. This chip has quad SPI and a 32K RX buffer.
I will be experimenting with it and the P2 as soon as I can get my hands on hardware. I will keep you all posted. The datasheet's registers are very similar to the W6100, so I am hoping the lift won't be too much.
--Terry
Comments
Quad SPI, and QPI, via smartpins needs some acrobatics. Placing the clock pin in the middle of the data pins is a must, so then it can be routed to all four smartpinB inputs.
The down side of doing that is it then precludes the streamer as an option since that requires the data output pins to be consecutively ordered.
So you basically have to choose up front if you want to invest in the performance of DMA'd streamer ops, or stick with managing four serial shifters while massaging the data back and forth between serial and parallel.
EDIT: On the other hand, it wouldn't be a big deal to include a few jumpers to the board layout to allow reordering of the clock and data pins. That would allow both code paths to be explored without needing two board designs.
Hope this helps the planning at least.
@ke4pjw Didn't your board use the 8-bit bus? That has to be fastest interface, right?
Just got some w6100io modules to hopefully enable the ethernet port on the PLC thing working on.
No sign of w6300io yet though...
Just plain SPI for me. Does bigger buffers help in that case? Guessing not, but can't hurt.
My board does both. SPI is only on one of the 12pin connectors and it is on the one that needs power. If you wire the io board up, my driver would work with it as it supports both parallel and SPI. Also, my driver is cogless, unless you are reading E1.31 data.
I never could get the speed fast enough in SPI mode for 40fps @ thousands pixels.
My only complaint about the W6100 is the poor UDP performance at 100mbps.
--Terry
I requested one of the W6300 samples from WizNet and they reached out via email today. I may have one in hand, later this month.
--Terry
So I have started on the Spinner Edge II with the W6300. Wiznet sent me some samples. I have a couple of the raw ICs and I also have 2 of their RP-2350 based boards. (Too bad I can't figure out what tools are needed to program them)
I will only implement QSPI on the SE II, as that is what they recommend for best performance. (I really want that 90Mbps)
Below is my (only checked over once) schematic. @evanh take a gander at the Quad SPI frame format. Is that unusual? Should I choose better CS and CLK pins? I think it would be helpful to have the nibble on a valid boundary to shift out data. I am not sure how or if those bit twiddling gymnastics could be performed by a smartpin.
Please feel free to throw rocks. If there is going to be a problem, I want to know about it up front.
Given that the instruction phase is sending 8 bits on QD0 with QD1-QD3 as don't care you can still make use of the streamer to send it all out in a contiguous block. You just need to distribute the 8 "I" bits into the streamed command - the MERGE instruction would let you group 8 bit instruction into nibbles and send it out with the LSB sending the data (although you'd need to reverse the 8 bits beforehand to send MSbit first, unless you setup the streamer to do the reordering). You'd first stream the instruction then the 16 bit address and 8 bit dummy and the real write data for writes, or for reads turn the bus around to read it back during the dummy step. Timing is everything but it's all doable. You need the nibble aligned on a 4 pin boundary if you use the streamer for highest performance. Other control pins can be anything. The clock would be generated by a smart pin and be some multiple of the P2 clock period. A 200MHz P2 could read up 100MB/s for example, although you can do it slower at 12.5MB/s and that still supports 100Mbps transfers.
Well, I guess I need to get a few of these built so I a can start poking at it.