@msrobots said:
one thing I would like to explore is to use the streamer, I have not found it yet but one last addition to the streamer modes was one that could stream in with a external clock.
Added for ADC/DAC pins to/from streamer but chip confirmed it works also without activating ADC/DAC.
Huh, I never knew about that at all. /me goes looking ...
EDIT: There is this but it doesn't look like a match due to it saying "per clock". Which I understand to mean sysclock:
Each cog has a 32-bit SCOPE data pipe which is intended to be used with smart pins configured to the 'scope' mode. The SCOPE data pipe continuously aggregates the lower bytes of RDPIN values from a 4-pin block, so that the streamer can record up to four time-aligned 8-bit ADC samples per clock.
I am 100% sure, even talked with chip about it somewhere around last year. Will ask at the next zoom meeting. Streaming in with external clock from pin to hub or lut.
@msrobots said:
I am 100% sure, even talked with chip about it somewhere around last year. Will ask at the next zoom meeting. Streaming in with external clock from pin to hub or lut.
Yes, I thought of using the streamer, but (like evanh) I can't see how to do it. If you can provide any details I'll give it a go.
@msrobots said:
Still thinking about that Ringbuffer concept @"Beau Schwabe" did with the P1...
I was ahead of my time - smirk
I think I was able to get a throughput in excess of 14 Meg per second, but I used 4 I/O lines each sending receiving a long variable.
The serial was basically 32N1 instead of the standard 8N1 .... One exception was that I used 2 start bits that were 1/2 of a period for synchronizing instead of 1 start bit.
So the 32N1 was basically ...
[s][s][D31][D30][D29][D28][D27][D26][D25][D24][D23][D22][D21][D20][D19][D18][D17][D16]
[D15][D14][D13][D12][D11][D10][D9][D8][D7][D6][D5][D4][D3][D2][D1][D0][S] ... 34 Clocks for 1 LONG
Compared to 8N1 ...
[S][D7][D6][D5][D4][D3][D2][D1][D0][S] ... 10 Clocks for 1 BYTE
... A long would require 40 Clocks, so doing it in 34 Clocks was a 15% speed increase, then doing it 4 longs at a time using 4 I/O's only required 8.5 Clocks for a 78% speed increase
Comments
Huh, I never knew about that at all. /me goes looking ...
EDIT: There is this but it doesn't look like a match due to it saying "per clock". Which I understand to mean sysclock:
I am 100% sure, even talked with chip about it somewhere around last year. Will ask at the next zoom meeting. Streaming in with external clock from pin to hub or lut.
Yes, I thought of using the streamer, but (like evanh) I can't see how to do it. If you can provide any details I'll give it a go.
Ross.
Only thing I remember it is some ADC mode and you do not activate the ADC pins, just leave them as digital.
will ask on Wednesday.
Mike
I was ahead of my time - smirk
I think I was able to get a throughput in excess of 14 Meg per second, but I used 4 I/O lines each sending receiving a long variable.
The serial was basically 32N1 instead of the standard 8N1 .... One exception was that I used 2 start bits that were 1/2 of a period for synchronizing instead of 1 start bit.
So the 32N1 was basically ...
[s][s][D31][D30][D29][D28][D27][D26][D25][D24][D23][D22][D21][D20][D19][D18][D17][D16]
[D15][D14][D13][D12][D11][D10][D9][D8][D7][D6][D5][D4][D3][D2][D1][D0][S] ... 34 Clocks for 1 LONG
Compared to 8N1 ...
[S][D7][D6][D5][D4][D3][D2][D1][D0][S] ... 10 Clocks for 1 BYTE
... A long would require 40 Clocks, so doing it in 34 Clocks was a 15% speed increase, then doing it 4 longs at a time using 4 I/O's only required 8.5 Clocks for a 78% speed increase
Ah, that's time or inverse speed. I would put 350% speed increase, or 4.5x the speed.