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Multimode SPI Implementation (SPIN2 + PASM) - Page 3 — Parallax Forums

Multimode SPI Implementation (SPIN2 + PASM)

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  • Thank you! @evanh

  • evanhevanh Posts: 15,126
    edited 2023-03-07 12:28

    I take it you got it to work then? I'm pretty certain now I never got round to testing those programs, which will be why I never posted them back then.

    The comments in spi_shift_out() haven't been adjusted to fit the code either. They're still mostly as per the spi_shift_in() it was initially copied from.

  • @evanh said:
    I take it you got it to work then? I'm pretty certain now I never got round to testing those programs, which will be why I never posted them back then.

    The comments in spi_shift_out() haven't been adjusted to fit the code either. They're still mostly as per the spi_shift_in() it was initially copied from.

    Yes,spi_shift_out() works properly.

  • evanhevanh Posts: 15,126

    Cool, thanks.

  • evanhevanh Posts: 15,126
    edited 2023-03-09 13:03

    Oops, I've incorrectly used CPOL. It's set in that program - which is performing as Mode 0 there but the convention is it should be Mode 2 or 3 when set. I'll work on tidying it up a little more ...

  • evanhevanh Posts: 15,126
    edited 2023-03-10 11:39

    Ha, turns out it doesn't make a lot of difference to a mode 0 master which polarity is used for shifting at lower speeds since the I/O lag effect places the MISO pin change plenty late enough to be classed as both SPI clock mode 0 and mode 1.

    Anyway, I've now detailed and partially compensated the lag as well as adding the CPHA option.

    EDIT: Damn, introduced a new bug by moving to a 32-bit shifter ... gone back to 16-bit, there was no need to change it ...

    EDIT2: Right, done a little testing this time. Dug up the original tester for a simulated master - I do now remember doing some last year. :) That's when I got those scope captures of the serial jitter between two boards - https://forums.parallax.com/discussion/comment/1544067/#Comment_1544067

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