Proposing a possible Gigatron remake using a P2
I may or may not build this, so please keep this in mind. I'm proposing this here in the effort of seeing if it is worthwhile for me to get a P2 board for this and to document my ideas. I could probably do just as much on my A7 board.
Now, I'd want to go beyond the original Gigatron in that multiple cogs would allow for better peripheral options. Others have cloned the Gigatron itself on a P2 and have 99% compatibility. I am more after improved performance over the original Gigatron, and for a long time, I proposed converting the vCPU software core in the Gigatron mode that it written in Gigatron native code into its own core, whether on an FPGA, using discrete parts, or on the P2.
The challenge here is that the vCPU is not a complete system in and of itself. Other things would need to be added. For the Gigatron, the native ROM sets up the memory map, creates the video display, manages I/O, and more. So I'd probably want a supervisor or setup cog to do the setup and use other cogs to handle standard I/O and storage I/O. Since everything is in separate cogs, there would need to be ways to sync the different processes. Sure, everything can communicate through hub RAM, so there would be no hardware races, but for a design that is split into different sections, there should be mechanisms such as pausing the vCPU core when desired for compatibility and performance-gating reasons (such as making the original games run.
As for things like file I/O which is weak on the original, such a design can improve upon this. There would be no reason to modulate the V-sync or use the address lines to speak to outside devices. There would be no need for a shift register in the critical path of the I/O. Most of the add-on cards could be replaced with P2 versions and implemented more appropriately for a P2.
So I think this could be a way to make a more usable system for running GT1 files and create a framework for other P2 experiments. So the vCPU core could be replaced with or working alongside a 6502 core, or other emulated cores, if not actual P2 native code.