How do you set 15K sink Input pin using PASM

Comments

• JonnyMac Posts: 8,926

  2021-09-24 18:31 edited 2021-09-24 18:48

  Easy-peasy

                  wrpin     ##P_LOW_15K, BTN
                  drvl      BTN
  
  check           testp     BTN                           wc
                  drvc      LED
                  jmp       #check
  
  
  BTN             long      21
  LED             long      56 
  

  You can make your posts more readable by putting three back-ticks (on ~ key) on the lines above and below your source code.
• Bob Drury Posts: 236

  2021-09-24 18:43

  Jon
  Thanks will try out
  Regards
  Bob (WRD)
• Bob Drury Posts: 236

  2021-09-24 21:54

  According to PASM Instruction SpreadSheet:
  WRPIN D/#,S/# - Set smart pin S/# mode to D/#, ack pin Set mode of smart pins S[10:6]+S[5:0]..S[5:0] to D,
  acknowledge smart pins. Wraps within A/B pins. Prior SETQ overrides S[10:6].

  D = %AAAA_BBBB_FFF_MMMMMMMMMMMMM_TT_SSSSS_0 is the Smart Pin Mode Setting

  Some Questions:

  1) What does S[10:6]+S[5:0]..S[5:0] to D,means? Shouldn't D be D[31:28] +D[27:24]+ D[23:21]+D[20:8]+D[7:6]+D[5:1]+D[0] to match AAAA_BBBB_FFF_MMMMMMMMMMMMM_TT_SSSSS_0 .

  2) ##P_LOW_15K What is ## saying (WRPIN D/#,S/#) D can only hold 9bits

  Regards and Thanks
  Bob (WRD)
• Rayman Posts: 13,892

  2021-09-24 22:43

  The ## is a shortcut for things like AuGS

  The other is a way to set multiple pins
• JonnyMac Posts: 8,926

  2021-09-24 23:02

  From page 121 of the P2 documentation

  
• Cluso99 Posts: 18,069

  2021-09-24 23:49

  @JonnyMac said:
  From page 121 of the P2 documentation

  

  Quick look at this and I thought this was in error (expecting to see AUGD). Then realised what the example meant. Probably docs should be expanded to show what it gets converted to....

    AUGD #($FFFF >>9)
    AND  address,#($FFFF & $1FF)
  
    AUGD #(far_away >>9)
    DJNZ reg,#(far_away & $1FF)
  

  Hope I got this correct
• Bob Drury Posts: 236

  2021-09-25 01:01

  Cluso99
  AUGS #n Queue #n to be used as upper 23 bits for next #S occurrence, so that the next 9-bit #S will be augmented to 32 bits.
  AUGD #n Queue #n to be used as upper 23 bits for next #D occurrence, so that the next 9-bit #D will be augmented to 32 bits.
  Is Queue a cog embedded CPU register ?
  With reference to "wrpin ##P_LOW_15K, BTN" what code would the compiler generate?
  If it is not a single register can you augment both D and S address "MOV ##D,##S" I think this would be helpful for Notes I am creating.
  Any help would be apreciated.
  Regards
  Bob (WRD)
• evanh Posts: 15,188

  2021-09-25 01:04 edited 2021-09-25 01:07

  The hidden Q register is separate from the two AUGx registers. All three are hidden special registers. Yes, both S and D can be extended together. There's some rules around also using ALTx, SETQ, and interrupt blocking.
• evanh Posts: 15,188

  2021-09-25 02:07 edited 2021-09-25 02:19

  Rules:

  • ALTx/SCA/XORO32 instructions have to be hard prefixed. They can only operate on the very next instruction.
  • AUGx normally affects the next instruction but will automatically extend over other AUGx and ALTx.
  • SETQ normally affects the next instruction but will automatically extend over other AUGx and ALTx.
  • Interrupts are postponed during a SETQ or AUGx or ALTx ... any instruction prefixing. Notably also for the duration of a REP loop and all WAITx instructions.
• evanh Posts: 15,188

  2021-09-25 02:28

  One side effect is ALTx instructions can't be AUGmented. It's not an issue in practise: D index is always a register and S mode is often a small value or is better off placed in a config register too.
• evanh Posts: 15,188

  2021-09-25 02:49 edited 2021-09-25 02:55

  Cluso,
  Those are both AUGS examples because it's the S field operand getting the supplemental extra bits:

    AND  address,##$FFFF
    DJNZ reg,##far_away
  
  

  expands to:

    AUGS #($FFFF >>9)
    AND  address,#($FFFF & $1FF)
  
    AUGS #(far_away >>9)
    DJNZ reg,#(far_away & $1FF)
  

  EDIT: I've called it "operand" because that'll be where the AUGmentation is occurring, at the input to the ALU. The S field is fixed at 9 bits wide.
• evanh Posts: 15,188

  2021-09-25 03:12 edited 2021-09-25 03:12

  So wrpin ##P_LOW_15K, btn expands to:

      augd  #(P_LOW_15K >>9)
      wrpin  #(P_LOW_15K & $1ff), btn
  
• Bob Drury Posts: 236

  2021-09-25 03:24

  evanh
  Lots of info there will add to my notes.
  Thanks
  Bob (WRD)
• evanh Posts: 15,188

  2021-09-25 03:30 edited 2021-09-25 03:57

  @"Bob Drury" said:
  WRPIN D/#,S/# - Set smart pin S/# mode to D/#, ack pin Set mode of smart pins S[10:6]+S[5:0]..S[5:0] to D, acknowledge smart pins. Wraps within A/B pins. Prior SETQ overrides S[10:6].

  D = %AAAA_BBBB_FFF_MMMMMMMMMMMMM_TT_SSSSS_0 is the Smart Pin Mode Setting

  Very easy to miss what Chip is saying in his concise descriptions. I've been writing questions for Chip to answer many a time, but when quoting the descriptions in my write-up it suddenly sinks in what he's actually stated. Needless to say I don't then asked the question.

  The key detail above is the opening Set smart pin S/# mode to D/#. Get that clear and the rest flows better. S is just for specifying which pins are written. D is mode being written.

  As for the initially cryptic S[10:6]+S[5:0]..S[5:0], that is precisely defining the encoding for a range of pins. What it says is a pin number range using the lower 6 bits of S operand for the base pin number plus an additional number of pins using bits 6 through 10 of S operand.

  And it's generally written reverse notation like that to match readable big-endian digit ordering. So then digit order doesn't go down the same rabbit-hole as little-endian byte ordering has.
• evanh Posts: 15,188

  2021-09-25 04:22 edited 2021-09-25 04:26

  As for opening question:

      wrpin (21 , P_LOW_15K) 'select P21 pull-down enable sets pin as a low
      pinlow(21) ' activate pin P21 as a low (out high enable off)
      repeat
          result0:=pinread(21)
          debug(udec(result0))
  

  translates to:

      wrpin  ##P_LOW_15K, #21
      drvl  #21
  .loop
      rdpin  pa, #21
      debug  (udec(pa))
      jmp  #.loop
  
• Cluso99 Posts: 18,069

  2021-09-25 04:40

  @evanh said:
  Cluso,
  Those are both AUGS examples because it's the S field operand getting the supplemental extra bits:

    AND  address,##$FFFF
    DJNZ reg,##far_away
  
  

  expands to:

    AUGS #($FFFF >>9)
    AND  address,#($FFFF & $1FF)
  
    AUGS #(far_away >>9)
    DJNZ reg,#(far_away & $1FF)
  

  EDIT: I've called it "operand" because that'll be where the AUGmentation is occurring, at the input to the ALU. The S field is fixed at 9 bits wide.

  Of course it’s AUGS, not AUGD. Need more coffee.
• evanh Posts: 15,188

  2021-09-25 05:57 edited 2021-09-25 06:00

  Oops, I got PINREAD() wrong. My inexperience with Spin showing again.

      wrpin  ##P_LOW_15K, #21
      drvl  #21
      mov  pa, #0
  .loop
      testp  #21  wc
      bitc  pa, #0
      debug  (udec(pa))
      jmp  #.loop
  
• evanh Posts: 15,188

  2021-09-25 06:35

  Duh! Jon had answered that one already.
• Bob Drury Posts: 236

  2021-09-25 22:27

  evanh
  For the following code seems to work the
  testp #21 wc
  bitc PinValue,#0
  Debug(udec(PinValue)) gives the status of Button 0 or 1

  This doesn' seem to work
  RDPIN PinValue,#21
  debug(udec(PinValue)) does not give the status of button remains 0

  Does RDPIN only work non logic configured smart pin?
  Regards and Thanks
  Bob (WRD)
• evanh Posts: 15,188

  2021-09-26 03:30

  Correct. Pin and Smartpin are two different things. They just happen to share IN, OUT, DIR and the config register. RDPIN/RQPIN/WXPIN/WYPIN are all for smartpin access only. WRPIN configures both.

  Have a good look at the I/O block diagram - https://forums.parallax.com/discussion/171420/smartpin-diagram/p1