How do you set 15K sink Input pin using PASM

Bob Drury

Using PB/LED Control 64006-ES (PB\LED module) with pins 16-23.
I want to set P21 to a sinking input to use PB with PASM . In spin the following Works:

con
_clkfreq = 200_000_000
Base_Pin = 16 'Base_Pin for PB/LED Control Board 64006-ES
PUB main()|result0
wrpin (21 , P_LOW_15K) 'select P21 pull-down enable sets pin as a low
pinlow(21) ' activate pin P21 as a low (out high enable off)
repeat
result0:=pinread(Base_Pin+5)
debug(udec(result0))
repeat

How do you do this in PASM? The pinlow command in spin I believe acivates the sink resistor.
I have been trying the following:

con
_clkfreq = 200_000_000
PUB main()
CALL(@SelectEvent)
repeat

Dat org 'this means COG ram I believe after stored after spin program
SelectEvent NOP
MOV D_WRPIN,CodeP_LOW_15K
WRPIN D_WRPIN,S_WRPIN
'( now what to enable sink resistor)
Loop NOP
TESTB INA,S_WRPIN WC
IF_C MOV CARRY,#1
IF_NC MOV CARRY,#0
debug(udec(CARRY))
JMP Loop
ret MOV CARRY,CARRY 'doesn't do anything
CARRY long 0
CodeP_LOW_15K long P_LOW_15K
D_WRPIN long 0
S_WRPIN long 21

regards and thanks
Bob (WRD)

JonnyMac

Easy-peasy

                wrpin     ##P_LOW_15K, BTN
                drvl      BTN

check           testp     BTN                           wc
                drvc      LED
                jmp       #check


BTN             long      21
LED             long      56 

You can make your posts more readable by putting three back-ticks (on ~ key) on the lines above and below your source code.

Bob Drury

Jon
Thanks will try out
Regards
Bob (WRD)

Bob Drury

According to PASM Instruction SpreadSheet:
WRPIN D/#,S/# - Set smart pin S/# mode to D/#, ack pin Set mode of smart pins S[10:6]+S[5:0]..S[5:0] to D,
acknowledge smart pins. Wraps within A/B pins. Prior SETQ overrides S[10:6].

D = %AAAA_BBBB_FFF_MMMMMMMMMMMMM_TT_SSSSS_0 is the Smart Pin Mode Setting

Some Questions:

1) What does S[10:6]+S[5:0]..S[5:0] to D,means? Shouldn't D be D[31:28] +D[27:24]+ D[23:21]+D[20:8]+D[7:6]+D[5:1]+D[0] to match AAAA_BBBB_FFF_MMMMMMMMMMMMM_TT_SSSSS_0 .

2) ##P_LOW_15K What is ## saying (WRPIN D/#,S/#) D can only hold 9bits

Regards and Thanks
Bob (WRD)

Rayman

The ## is a shortcut for things like AuGS

The other is a way to set multiple pins

JonnyMac

From page 121 of the P2 documentation

Cluso99

@JonnyMac said:
From page 121 of the P2 documentation

Quick look at this and I thought this was in error (expecting to see AUGD). Then realised what the example meant. Probably docs should be expanded to show what it gets converted to....

  AUGD #($FFFF >>9)
  AND  address,#($FFFF & $1FF)

  AUGD #(far_away >>9)
  DJNZ reg,#(far_away & $1FF)

Hope I got this correct

Bob Drury

Cluso99
AUGS #n Queue #n to be used as upper 23 bits for next #S occurrence, so that the next 9-bit #S will be augmented to 32 bits.
AUGD #n Queue #n to be used as upper 23 bits for next #D occurrence, so that the next 9-bit #D will be augmented to 32 bits.
Is Queue a cog embedded CPU register ?
With reference to "wrpin ##P_LOW_15K, BTN" what code would the compiler generate?
If it is not a single register can you augment both D and S address "MOV ##D,##S" I think this would be helpful for Notes I am creating.
Any help would be apreciated.
Regards
Bob (WRD)

evanh

The hidden Q register is separate from the two AUGx registers. All three are hidden special registers. Yes, both S and D can be extended together. There's some rules around also using ALTx, SETQ, and interrupt blocking.

evanh

Rules:

• ALTx/SCA/XORO32 instructions have to be hard prefixed. They can only operate on the very next instruction.
• AUGx normally affects the next instruction but will automatically extend over other AUGx and ALTx.
• SETQ normally affects the next instruction but will automatically extend over other AUGx and ALTx.
• Interrupts are postponed during a SETQ or AUGx or ALTx ... any instruction prefixing. Notably also for the duration of a REP loop and all WAITx instructions.

evanh

One side effect is ALTx instructions can't be AUGmented. It's not an issue in practise: D index is always a register and S mode is often a small value or is better off placed in a config register too.

evanh

Cluso,
Those are both AUGS examples because it's the S field operand getting the supplemental extra bits:

  AND  address,##$FFFF
  DJNZ reg,##far_away

expands to:

  AUGS #($FFFF >>9)
  AND  address,#($FFFF & $1FF)

  AUGS #(far_away >>9)
  DJNZ reg,#(far_away & $1FF)

EDIT: I've called it "operand" because that'll be where the AUGmentation is occurring, at the input to the ALU. The S field is fixed at 9 bits wide.

evanh

So wrpin ##P_LOW_15K, btn expands to:

    augd  #(P_LOW_15K >>9)
    wrpin  #(P_LOW_15K & $1ff), btn

Bob Drury

evanh
Lots of info there will add to my notes.
Thanks
Bob (WRD)

evanh

@"Bob Drury" said:
WRPIN D/#,S/# - Set smart pin S/# mode to D/#, ack pin Set mode of smart pins S[10:6]+S[5:0]..S[5:0] to D, acknowledge smart pins. Wraps within A/B pins. Prior SETQ overrides S[10:6].

D = %AAAA_BBBB_FFF_MMMMMMMMMMMMM_TT_SSSSS_0 is the Smart Pin Mode Setting

Very easy to miss what Chip is saying in his concise descriptions. I've been writing questions for Chip to answer many a time, but when quoting the descriptions in my write-up it suddenly sinks in what he's actually stated. Needless to say I don't then asked the question.

The key detail above is the opening Set smart pin S/# mode to D/#. Get that clear and the rest flows better. S is just for specifying which pins are written. D is mode being written.

As for the initially cryptic S[10:6]+S[5:0]..S[5:0], that is precisely defining the encoding for a range of pins. What it says is a pin number range using the lower 6 bits of S operand for the base pin number plus an additional number of pins using bits 6 through 10 of S operand.

And it's generally written reverse notation like that to match readable big-endian digit ordering. So then digit order doesn't go down the same rabbit-hole as little-endian byte ordering has.

evanh

As for opening question:

    wrpin (21 , P_LOW_15K) 'select P21 pull-down enable sets pin as a low
    pinlow(21) ' activate pin P21 as a low (out high enable off)
    repeat
        result0:=pinread(21)
        debug(udec(result0))

translates to:

    wrpin  ##P_LOW_15K, #21
    drvl  #21
.loop
    rdpin  pa, #21
    debug  (udec(pa))
    jmp  #.loop

Cluso99

@evanh said:
Cluso,
Those are both AUGS examples because it's the S field operand getting the supplemental extra bits:

  AND  address,##$FFFF
  DJNZ reg,##far_away

expands to:

  AUGS #($FFFF >>9)
  AND  address,#($FFFF & $1FF)

  AUGS #(far_away >>9)
  DJNZ reg,#(far_away & $1FF)

EDIT: I've called it "operand" because that'll be where the AUGmentation is occurring, at the input to the ALU. The S field is fixed at 9 bits wide.

Of course it’s AUGS, not AUGD. Need more coffee.

evanh

Oops, I got PINREAD() wrong. My inexperience with Spin showing again.

    wrpin  ##P_LOW_15K, #21
    drvl  #21
    mov  pa, #0
.loop
    testp  #21  wc
    bitc  pa, #0
    debug  (udec(pa))
    jmp  #.loop

evanh

Duh! Jon had answered that one already.

Bob Drury

evanh
For the following code seems to work the
testp #21 wc
bitc PinValue,#0
Debug(udec(PinValue)) gives the status of Button 0 or 1

This doesn' seem to work
RDPIN PinValue,#21
debug(udec(PinValue)) does not give the status of button remains 0

Does RDPIN only work non logic configured smart pin?
Regards and Thanks
Bob (WRD)

evanh

Correct. Pin and Smartpin are two different things. They just happen to share IN, OUT, DIR and the config register. RDPIN/RQPIN/WXPIN/WYPIN are all for smartpin access only. WRPIN configures both.

Have a good look at the I/O block diagram - https://forums.parallax.com/discussion/171420/smartpin-diagram/p1