W25Q128JV SPI Flash on P2 - dual SPI operation?
I was just looking at the SPI flash used on the P2-EVAL and reading it can offer a dual SPI mode where data is input/output on two pins and can also be clocked at high speed up to 133MHz.
At first I got a little excited by this but then unfortunately found it has been wired in reverse data order to what the streamer natively uses, with IO-1 on pin 58 and IO-0 pin 59. This means any data streamed into it will be reversed to the natural byte order. Even the streamer's re-ordering capability doesn't solve this.
Eg, if the data output by the Flash to both pins is in this sequence:
I/O-0 I/O-1 D6 D7 D4 D5 D2 D3 D0 D1
Then it will be assembled into one of the following bytes and written into HUB memory depending on the "a" bit setting in the streamer.
b7 ..... b0 D0 D1 D2 D3 D4 D5 D6 D7 (needs reversing per byte) D6 D7 D4 D5 D2 D3 D0 D1 (totally messed up, needs bit pair swaps)
It the two pins had been wired the other way, we would have been able to stream the data in/out of the P2 HUB at high speed (~33MB/s using 133MHz) with little COG intervention once the DUAL SPI transfer was initiated. After all the original discussion on this ages ago, it almost feels like it was arbitrary to wire in this way in the end which is a pity.
Maybe some bit banging as Peter Jakacki has done for the SD can get the rate up higher...?
Also, even if P56, P57 get wired on custom boards to complete the Quad SPI data group, the nibble would still be in reversed bit order. Can't win.
The only way to make it work is to lay out the memory in the reversed bit order when writing to flash, but keep it correct for the boot image portion. That bit order is now locked into the boot ROM.