Small RISC-V chips

Comments

• jmg Posts: 15,191

  2020-10-10 00:52

  There was an interesting die image of this family posted here
  https://www.eevblog.com/forum/microcontrollers/risc-v-microcontrollers-from-gigadevice/msg3027160/#msg3027160
  
  Appears to have a stacked flash die.
• Cluso99 Posts: 18,069

  2020-10-10 21:05 edited 2020-10-10 21:07

  Peter,
  Nice find! Did it come with the plastic case too?
  
  Would be nice to find a cheap micro that can connect a USB keyboard and USB mouse to a serial port(s) for connecting into a P1 or P2 using 1 or 2 pins.
• Peter Jakacki Posts: 10,193

  2020-10-10 23:09 edited 2020-10-10 23:12

  Yes, it had the snap together case. I made the mistake of connecting up the USB-C to power it and trying to load Forth onto it via the pin header serial which has the default bootloader, but it wouldn't work. Finally I disconnected the USB-C and used the LED voltage drop trick for 3.3ish volts and it worked.
  
  I have been pouring over RISC-V documents and simulators and lecture notes on assembly language etc and the ISA is indeed strange. There are no condition codes and the conditional jumps do the "compare" and branch. The equivalent to augs to load 32-bits but not is lui which loads the upper 20 bits directly into the register and so therefore you need to do an addi or similar to add in the lsbs, although there is a corner case due to automatic sign extension.
  To load register x10 with "0xDEADBEEF" (corner case exeception)

  lui x10,0xDEADC
  addi x10,x10,0xEEF
  

  It's not as pretty as I had hoped, but it works. So much nicer always having 32-1 registers usable instead of the Cortex crippling registers.
  
  The USB on the GD32VF103 is OTG so I can also host devices.
  
  @jmg - Interesting that they must load Flash into hidden RAM for zero wait states then.
  
  
  
• Ariba Posts: 2,693

  2020-10-11 00:38 edited 2020-10-11 00:39

  Peter Jakacki wrote: »

  I have been pouring over RISC-V documents and simulators and lecture notes on assembly language etc and the ISA is indeed strange. There are no condition codes and the conditional jumps do the "compare" and branch. The equivalent to augs to load 32-bits but not is lui which loads the upper 20 bits directly into the register and so therefore you need to do an addi or similar to add in the lsbs, although there is a corner case due to automatic sign extension.
  To load register x10 with "0xDEADBEEF" (corner case exeception)

  lui x10,0xDEADC
  addi x10,x10,0xEEF
  

  It's not as pretty as I had hoped, but it works. So much nicer always having 32-1 registers usable instead of the Cortex crippling registers.

  
  for sure you can also write:

    li  x10, #0xDEADBEEF
  

  and the assembler will generate the LUI and the ADDI instruction for you, just like
  mov reg,##$DEADBEEF with P2 assembly.
  
  Andy
  
• Peter Jakacki Posts: 10,193

  2020-10-11 00:45 edited 2020-10-11 00:49

  @Ariba - yes, there are lots of pseudo instructions that take care of these things. I always like to understand it without all the extra layers added or hidden.
  For instance, there is no move register or a jump instruction etc but they use the encoding to achieve this in one instruction whereas others such as "long 32-bit immediate" must use two instructions and compensate for sign extension.
  
  Since I like to write a Forth that really groks the ISA, I need to understand it well so that I can even write my own assembler if need be which is sometimes necessary just to get it to work the way you need.
  
  After having worked with ARM and Prop conditional ALU operations, I am once again having to work with none
  
• Maciek Posts: 692

  2021-01-04 17:24

  I know you are terribly busy but since that is a permanent state then I thought I'd better ask now and wait patiently for an answer.
  
  Do you have any update for us poor souls ?
  
  I saw another Risc-V module on your microMat board in the P2D2 thread so hopefully you didn't abandoned that project, did you ?