Small RISC-V chips

Peter Jakacki

I've got a few of these Sipeed Longan Nano - RISC-V GD32VF103CBT6 development boards which come with a 108MHz 32-bit RISC-V core packed with all the peripherals including USB and 128kB Flash and 32kB RAM. The board also has a 160x96 color tft and uSD and a USB-C connector etc.

I want to use these in the next generation of USB serial and support chips as there is one available in QFN36 but even the 7x7mm LQFP48 is not bad.
At the moment I have managed to install all the dev tools and working with PlatformIO in the VS IDE. I've used a RISC-V version of mecrisp Forth to talk to the board but I will develop a Forth along Tachyon lines for it so I can drop a chip onto a board and program it serially via the host P1/P2 as required.

I have USB serial dongle connected to the pin header for this and needed 3.3V but my dongle only had 5V, so I took a chance that the current wouldn't be too high and inserted a red LED from 5V to 3.3V (about 1.8V drop) and it works fine and the LED is still working.

fibos 
fibo(6 )  = 8 
fibo(7 )  = 13 
fibo(8 )  = 21 
fibo(9 )  = 34 
fibo(10 )  = 55 
fibo(11 )  = 89 
fibo(12 )  = 144 
fibo(13 )  = 233 
fibo(14 )  = 377 
fibo(15 )  = 610 
fibo(16 )  = 987 
fibo(17 )  = 1597 
fibo(18 )  = 2584 
fibo(19 )  = 4181 
fibo(20 )  = 6765 
fibo(21 )  = 10946 
fibo(22 )  = 17711 
fibo(23 )  = 28657 
fibo(24 )  = 46368 
fibo(25 )  = 75025 
fibo(26 )  = 121393 
fibo(27 )  = 196418 
fibo(28 )  = 317811 
fibo(29 )  = 514229 
fibo(30 )  = 832040 
fibo(31 )  = 1346269 
fibo(32 )  = 2178309                                        
fibo(33 )  = 3524578                                        
fibo(34 )  = 5702887                                        
fibo(35 )  = 9227465                                        
fibo(36 )  = 14930352                                       
fibo(37 )  = 24157817                                       
fibo(38 )  = 39088169                                       
fibo(39 )  = 63245986                                       
fibo(40 )  = 102334155                                      
fibo(41 )  = 165580141                                      
fibo(42 )  = 267914296                                      
fibo(43 )  = 433494437                                      
fibo(44 )  = 701408733                                      
fibo(45 )  = 1134903170                                     
fibo(46 )  = 1836311903  ok.

Here's a photo next to an older P2D2

jmg

There was an interesting die image of this family posted here
https://www.eevblog.com/forum/microcontrollers/risc-v-microcontrollers-from-gigadevice/msg3027160/#msg3027160

Appears to have a stacked flash die.

Cluso99

Peter,
Nice find! Did it come with the plastic case too?

Would be nice to find a cheap micro that can connect a USB keyboard and USB mouse to a serial port(s) for connecting into a P1 or P2 using 1 or 2 pins.

Peter Jakacki

Yes, it had the snap together case. I made the mistake of connecting up the USB-C to power it and trying to load Forth onto it via the pin header serial which has the default bootloader, but it wouldn't work. Finally I disconnected the USB-C and used the LED voltage drop trick for 3.3ish volts and it worked.

I have been pouring over RISC-V documents and simulators and lecture notes on assembly language etc and the ISA is indeed strange. There are no condition codes and the conditional jumps do the "compare" and branch. The equivalent to augs to load 32-bits but not is lui which loads the upper 20 bits directly into the register and so therefore you need to do an addi or similar to add in the lsbs, although there is a corner case due to automatic sign extension.
To load register x10 with "0xDEADBEEF" (corner case exeception)

lui x10,0xDEADC
addi x10,x10,0xEEF

It's not as pretty as I had hoped, but it works. So much nicer always having 32-1 registers usable instead of the Cortex crippling registers.

The USB on the GD32VF103 is OTG so I can also host devices.

@jmg - Interesting that they must load Flash into hidden RAM for zero wait states then.

Ariba

Peter Jakacki wrote: »

I have been pouring over RISC-V documents and simulators and lecture notes on assembly language etc and the ISA is indeed strange. There are no condition codes and the conditional jumps do the "compare" and branch. The equivalent to augs to load 32-bits but not is lui which loads the upper 20 bits directly into the register and so therefore you need to do an addi or similar to add in the lsbs, although there is a corner case due to automatic sign extension.
To load register x10 with "0xDEADBEEF" (corner case exeception)

lui x10,0xDEADC
addi x10,x10,0xEEF

It's not as pretty as I had hoped, but it works. So much nicer always having 32-1 registers usable instead of the Cortex crippling registers.

for sure you can also write:

  li  x10, #0xDEADBEEF

and the assembler will generate the LUI and the ADDI instruction for you, just like
mov reg,##$DEADBEEF with P2 assembly.

Andy

Peter Jakacki

@Ariba - yes, there are lots of pseudo instructions that take care of these things. I always like to understand it without all the extra layers added or hidden.
For instance, there is no move register or a jump instruction etc but they use the encoding to achieve this in one instruction whereas others such as "long 32-bit immediate" must use two instructions and compensate for sign extension.

Since I like to write a Forth that really groks the ISA, I need to understand it well so that I can even write my own assembler if need be which is sometimes necessary just to get it to work the way you need.

After having worked with ARM and Prop conditional ALU operations, I am once again having to work with none

Maciek

I know you are terribly busy but since that is a permanent state then I thought I'd better ask now and wait patiently for an answer.

Do you have any update for us poor souls ?

I saw another Risc-V module on your microMat board in the P2D2 thread so hopefully you didn't abandoned that project, did you ?