Prop-2 %01111 "Count A-input highs." How does it work?
JonTitus
Posts: 193
in Propeller 2
I have a short program (below) that runs and displays the eight LSBs of the RQPIN data on LEDs. Does this mode count the system-clock periods that A is high? Or does it count the number of times the A input went to a logic-1 state. The values I get seem random. The %01110 mode that counts signal edges worked fine and incremented and decremented the count as expected. Switches are debounced and show clean signals on a scope.
'Count A-input highs
A_in = 53 'Pin P53
'B input at pin P54 (not used here)
dat org
mov dira, ##$FF 'Set P7..P0 as outputs for LEDs
dirl #A_in
wrpin A_in_mode, #A_in 'Set up mode for pin P53
wxpin ##$773_5940, #A_in 'Set for continuous count 5-sec, 25 MHz clock
wypin #0, #A_in 'Count only A-input high states.
dirh #A_in 'Enable Smart Pin
.loop rqpin my_data, #A_in 'Get count
mov outa, my_data 'send to LEDs
jmp #.loop 'Loop to get new count
A_in_mode long %0000_0001_000_0000000000000_00_01111_0
my_data long 0
Comments
The pin cell is Counter+Capture with user choices on
Clock (.clk), Capture (.cap), Capture and clear (.capc) Clock Enable for a gated counter (.ce)
My reading of this mode is :
.clk = SysCLK
.ce = A_in ie increments when A_in is high
.capc = SysCLK/X, - every 5 seconds, total is captured, and counter 'clears'.
Testing this with a button will be tricky, because the phase of that 5s window varies and a button press that crosses a 5s boundary will accumulate in two reading windows.
If you want a button for simplicity, maybe a LED could show the 5s so the user can self-sync.
Holding a button down for ~20 seconds, should read 4 $773_5940 results and the first and last readings will be less & depend on the phase of the capture with the button.
Displaying this on LEDs will not be easy, 0x07735940 = 0b 0111 0111 0011 0101 1001 0100 0000
Maybe you could shift to get upper 3 bits, and covert to a bar-graph ?
A bit less than 5 seconds could make this more responsive ? 1~2 seconds maybe ?
So, yes, it accumulates sysclocks while A input is high. There is four such counter modes:
' Mode 011111 ' Synchronous serial transmission (SPI) of system-clock periods, Rev. 4, 06-16-2020 at 1747H MDT ' Positive trigger on the SPI clockpositive edge-trigger (Jon Titus) CON clkout = 40 ' Pin P40 'Transmitter's clock out, to P31 txout = 41 ' Pin P41 'Transmitter data out, to P30 A_in = 53 ' Pin P53 dat org 0 dirl #txout 'Transmitter setup wrpin sync_tx_mode, #txout 'Set sync tx mode for pin 41 wxpin #%1_11111, #txout 'Set up stop/start mode, X[5] = 1, 32 bits (31 + 1) dirh #txout 'Enable transmitter output dirl #clkout 'Clock output setup wrpin clock_mode, #clkout 'Set pin as transition-output mode wxpin ##$1000, #clkout 'Set base period for transition output dirh #clkout 'Enable clock-output dirl #A_in 'Count A-input highs wrpin A_in_mode, #A_in 'Set up mode for pin P53 wxpin ##$17D_7840, #A_in 'Set for continuous count 1-sec, 25 MHz clock wypin #0, #A_in 'Count only A-input high states. dirh #A_in 'Enable Smart Pin .test_loop nop testp #A_in wc ' use waitx ##100_000 for testing nop if_nc jmp #.test_loop 'If no C flag, repeat testing rdpin rcvd_data, #A_in 'Found carry bit set, get data wypin rcvd_data, #txout 'rcvd_data to send out SPI wypin #64, #clkout 'Start clock, transmit data nop jmp #.test_loop '===================================== A_in_mode long %0000_0001_000_0000000000000_00_01111_0 rcvd_data long 0 sync_tx_mode long %0000_1111_000_0000000000000_01_11100_0 'Positive-edge clock mode clock_mode long %0000_0000_000_000000_0_000000_01_00101_0 'Clock-mode '====================================The reason is the tx smartpin is sensitive to any transitions on the clock pin. If the clock smartpin is setup after the tx smartpin, then some conditions can trigger a tx bit-shift upon clock init. This throws the word ordering off by one bit, which can be very confusing for the unsuspecting developer.