Back in the heyday of the Z80 we would occasionally need to single-step the chip to chase odd bugs. After booting at a normal speed, the clock would then be switched-over to a bounceless pushbutton or a (very slow) oscillator. As long as the RAM was static RAM, this worked fine. The chip didnt care.
Can this same strategy be used on the Prop1 (assuming we dont care about upsetting any timing-critical external components and we use a direct/non-pll clock mode)? I know the Prop1 works fine at 32khz, but will the internals hold-up to very long pauses between clock pulses? What about the Prop2?