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ADC Sampling Breakthrough

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  • Cluso99Cluso99 Posts: 18,063
    cgracey wrote: »
    Roy Eltham wrote: »
    Chip,
    Is this a change to just verilog stuff? Or does this require changes to the custom laid out pad stuff? I think that is Cluso's concern (and mine).

    It is just Verilog.
    It's the noise floor that's my question. Isn't this the custom laid out pad stuff?

    IMHO the fix (Sincx filters) should be in software, not Verilog expansion to the smart pins.

    A 16 bit ADC that has the lower 3-4 bits unusable, is still only 12 usable bits, no matter how you slice it.

    Sorry to be so blunt... but please get on to something that matters to all users, not just a few. Chip, please, you really need to prioritise the important bits first, not the fun bits.
  • cgraceycgracey Posts: 13,853
    Roy Eltham wrote: »
    Okay, that seems better (I think :) ). Getting 16bit samples at ~700kHz (180Mhz at 256sclk per) would be a pretty great feature.

    What is the number of clocks needed for 8, 10, and 12bit equivalent samples?

    8 takes 16 clocks.
    10 takes 32 clocks.
    12 takes 64 clocks.

    Bits = 2 * Log2(clocks)
  • cgraceycgracey Posts: 13,853
    Cluso99 wrote: »
    cgracey wrote: »
    Roy Eltham wrote: »
    Chip,
    Is this a change to just verilog stuff? Or does this require changes to the custom laid out pad stuff? I think that is Cluso's concern (and mine).

    It is just Verilog.
    It's the noise floor that's my question. Isn't this the custom laid out pad stuff?

    IMHO the fix (Sincx filters) should be in software, not Verilog expansion to the smart pins.

    A 16 bit ADC that has the lower 3-4 bits unusable, is still only 12 usable bits, no matter how you slice it.

    So, then do a 12-bit conversion in 64 clocks, instead of 4,096. For this to work, the integrator needs to be in hardware, running continuously.
    Sorry to be so blunt... but please get on to something that matters to all users, not just a few. Chip, please, you really need to prioritise the important bits first, not the fun bits.

    I think speeding up ADC conversions is pretty important. Plus, it's fun. Saving power will be fun, too. All coming soon.
  • Cluso99Cluso99 Posts: 18,063
    ADC - a thought...

    Let's say we can read an ADC pin reliably at 8 bits resolution.
    Now, lets connect that input signal to 4 pins. May have to use some resistor/buffer scheme - I am not an analog guru so I don't know.

    Now, setup the first pin as a 1/4 divider, the second as a 2/4 (1/2) divider, and the third as a 3/4 divider, and the last as a 1:1.

    Reading these in parallel should give 8 bits on the forth pin. Use that pin to tell which divider pin to use to get a more detailed 8 bit resolution. That pin also gives another 2 bits, since it has been scaled to a 1/4 resolution. Since these measurements were done in parallel, we have just expanded our depth 2 bits.
    Most micros cannot do this because the ADCs are mixed to one physical ADC.

    Wouldn't this work? Only software involved.
  • Is is reasonable to connect the same signal to 2 pins and sample them interleaved such that you get double the sampling rate?
    Or is this Sinc3 stuff causing the pins to be sync's to the system clock such that the samples would not be interleave-able?
  • jmgjmg Posts: 14,979
    Cluso99 wrote: »
    IMHO the fix (Sincx filters) should be in software, not Verilog expansion to the smart pins.

    They are in software, it's just that software happens to be Verilog :)
    There is a reason for that, the adders need to act every sysclock, on all 3 adders. Opcodes simply cannot manage that.
    The stuff that can be done using opcodes, is being done using opcodes.
    Cluso99 wrote: »
    A 16 bit ADC that has the lower 3-4 bits unusable, is still only 12 usable bits, no matter how you slice it.
    That's true of the internal ADC, but notice there are external ADCs that can use this same filter, in wide commercial use in Motor Drivers / UPS / Inverter applications.
    That's a pretty good space to be pushing P2 into.

    The filter also gives more useful readings per second, and that will matter to all users...

  • cgraceycgracey Posts: 13,853
    Roy Eltham wrote: »
    Is is reasonable to connect the same signal to 2 pins and sample them interleaved such that you get double the sampling rate?
    Or is this Sinc3 stuff causing the pins to be sync's to the system clock such that the samples would not be interleave-able?

    You could interleave them, but there are offset differences between the ADCs that would have to be dealt with. At high resolutions, there may also be scale differences to deal with.
  • cgraceycgracey Posts: 13,853
    So, I tried sign-extending the lower accumulators from lower bits and it doesn't work. It seems that all acc's in the integrator must be the same bit length. Any ideas?
  • jmgjmg Posts: 14,979
    cgracey wrote: »
    So, I tried sign-extending the lower accumulators from lower bits and it doesn't work. It seems that all acc's in the integrator must be the same bit length. Any ideas?

    I guess that's the proof. Worth a try.
    Were you able to at least make the first stage an enabled counter ? Should be smaller than a full adder ?
  • cgracey wrote: »
    So, I tried sign-extending the lower accumulators from lower bits and it doesn't work. It seems that all acc's in the integrator must be the same bit length. Any ideas?

    Thanks for trying, Chip. This confirms that if you add a stage you must increase all the previous stages to match that width. I don't know what the sign-extension in the PDF is referring to.

    How many counters and adders are there in a smart pin? A counter will suffice for acc1. How about re-using the adders+registers for acc2 and acc3 as counters in other pin modes and getting rid of some of the counter logic?
  • jmgjmg Posts: 14,979
    TonyB_ wrote: »
    How many counters and adders are there in a smart pin? A counter will suffice for acc1. How about re-using the adders+registers for acc2 and acc3 as counters in other pin modes and getting rid of some of the counter logic?
    The NCO mode must have a wide adder, so that leaves acc3 ?
  • evanhevanh Posts: 13,818
    In that IEEE paper that James linked, the oldest reference is to a 1981 paper! https://forums.parallax.com/discussion/comment/1455033/#Comment_1455033

    In section 4 there is this statement, but without explanation: "It also turn out that Bout bits are needed for each integrator and comb stage."

  • cgraceycgracey Posts: 13,853
    jmg wrote: »
    cgracey wrote: »
    So, I tried sign-extending the lower accumulators from lower bits and it doesn't work. It seems that all acc's in the integrator must be the same bit length. Any ideas?

    I guess that's the proof. Worth a try.
    Were you able to at least make the first stage an enabled counter ? Should be smaller than a full adder ?

    Since it can only have one added to it, I think it winds up being a gated counter, right?
  • cgraceycgracey Posts: 13,853
    evanh wrote: »
    In that IEEE paper that James linked, the oldest reference is to a 1981 paper! https://forums.parallax.com/discussion/comment/1455033/#Comment_1455033

    In section 4 there is this statement, but without explanation: "It also turn out that Bout bits are needed for each integrator and comb stage."

    That's a bummer. Oh, well. It's great that it works, at all!
  • cgraceycgracey Posts: 13,853
    jmg wrote: »
    TonyB_ wrote: »
    How many counters and adders are there in a smart pin? A counter will suffice for acc1. How about re-using the adders+registers for acc2 and acc3 as counters in other pin modes and getting rid of some of the counter logic?
    The NCO mode must have a wide adder, so that leaves acc3 ?

    Yes, the NCO mode has a wide adder. Let me see, if I make the SINC3 use the same registers, if it collapses some logic.
  • cgraceycgracey Posts: 13,853
    TonyB_ wrote: »
    cgracey wrote: »
    So, I tried sign-extending the lower accumulators from lower bits and it doesn't work. It seems that all acc's in the integrator must be the same bit length. Any ideas?

    Thanks for trying, Chip. This confirms that if you add a stage you must increase all the previous stages to match that width. I don't know what the sign-extension in the PDF is referring to.

    How many counters and adders are there in a smart pin? A counter will suffice for acc1. How about re-using the adders+registers for acc2 and acc3 as counters in other pin modes and getting rid of some of the counter logic?

    There are counters implemented somewhat differently in each smart pin mode. By making them use the same inputs and outputs, it might save some logic. We'll see.
  • cgracey wrote: »
    evanh wrote: »
    In that IEEE paper that James linked, the oldest reference is to a 1981 paper! https://forums.parallax.com/discussion/comment/1455033/#Comment_1455033

    In section 4 there is this statement, but without explanation: "It also turn out that Bout bits are needed for each integrator and comb stage."

    That's a bummer. Oh, well. It's great that it works, at all!

    Does bit 29 of the 30-bit accumulator3 go to bit 31 of acc3 in the differentiator?
  • evanhevanh Posts: 13,818
    The diff stage in the existing Sinc1 also is full 32-bit adder, so that mode has two 32-bit adders.
  • cgraceycgracey Posts: 13,853
    TonyB_ wrote: »
    cgracey wrote: »
    evanh wrote: »
    In that IEEE paper that James linked, the oldest reference is to a 1981 paper! https://forums.parallax.com/discussion/comment/1455033/#Comment_1455033

    In section 4 there is this statement, but without explanation: "It also turn out that Bout bits are needed for each integrator and comb stage."

    That's a bummer. Oh, well. It's great that it works, at all!

    Does bit 29 of the 30-bit accumulator3 go to bit 31 of acc3 in the differentiator?

    No, should it? That would make the overall output signed, right?
  • evanhevanh Posts: 13,818
    It would ruin the circular tracking. Which will be why they all have to be the same size.

  • cgraceycgracey Posts: 13,853
    edited 2018-11-27 01:20
    I've made the NCO module adder generate a discrete Z[31:0]+Y[31:0] sum that the compiler should recognize as also existing in the SINC3 module (as Z[29:0] + Y[29:0]). Before, the NCO mux'd in what was going to be added to Z. This should help reduce logic if SINC3 is implemented. Compiling now...
  • evanhevanh Posts: 13,818
    Oh, I see, X[31:0] period setting will be a countdown timer. So only a zero equality to test. No second adder in the Sinc1 mode.

  • cgraceycgracey Posts: 13,853
    Guys, maybe Saucy already spelled it out, but what's the best way to get 8-bit quality samples on every clock? This is something that the streamer can do economically.
  • cgraceycgracey Posts: 13,853
    edited 2018-11-27 01:28
    Okay, the compile just finished. It didn't make any difference!

    I think the compiler is already crunching things down pretty well.
  • evanhevanh Posts: 13,818
    edited 2018-11-27 01:30
    Erna gave an alternative, window of just 11 clocks, but it was expensive as hell. I think Sinc8 is likely the smallest.

  • cgracey wrote: »
    TonyB_ wrote: »
    cgracey wrote: »
    evanh wrote: »
    In that IEEE paper that James linked, the oldest reference is to a 1981 paper! https://forums.parallax.com/discussion/comment/1455033/#Comment_1455033

    In section 4 there is this statement, but without explanation: "It also turn out that Bout bits are needed for each integrator and comb stage."

    That's a bummer. Oh, well. It's great that it works, at all!

    Does bit 29 of the 30-bit accumulator3 go to bit 31 of acc3 in the differentiator?

    No, should it? That would make the overall output signed, right?

    If acc3 is negative in the integrator, shouldn't it also be negative in the differentiator? It's something different to try with sign-extending.
  • evanhevanh Posts: 13,818
    The values aren't specifically signed. It's just a circle that goes round and round, that's why two's-complement suits it.

  • evanhevanh Posts: 13,818
    From my school days: The integral of a sine function is a cosine function. The integral of a cosine function is a sine function.

  • cgraceycgracey Posts: 13,853
    Here is the SINC3 code. Note that the smart pin mux's in one of these files and gives it access to the 16 + 3*32 flops and uses its outputs.

    I haven't run this, yet, and I need to look it over carefully before trying it, but you can get the idea of how it works. Note that every single flop is being used.


    892 x 1939 - 51K
  • jmgjmg Posts: 14,979
    cgracey wrote: »
    I've made the NCO module adder generate a discrete Z[31:0]+Y[31:0] sum that the compiler should recognize as also existing in the SINC3 module (as Z[29:0] + Y[29:0]). Before, the NCO mux'd in what was going to be added to Z. This should help reduce logic if SINC3 is implemented. Compiling now...
    cgracey wrote: »
    Okay, the compile just finished. It didn't make any difference!

    I think the compiler is already crunching things down pretty well.

    Is there an easy way to confirm it has shared the adder between the 2 modes, as hoped ?
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