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  • Cluso99Cluso99 Posts: 18,062
    A simple google search has turned up these...

    May 6, 2014 - OnSemi ONC18 qualified IP: ultra-low power oscillator and very-small footprint OTP memory

    March 31, 2011 – Sidense Corp., a leading developer of Logic Non-Volatile Memory (LNVM) one-time programmable (OTP) memory IP cores, and ON Semiconductor (Nasdaq: ONNN), a premier supplier of high performance silicon solutions for energy efficient electronics, have announced that Sidense has ported its 180 nanometer (nm) OTP memory SLP product line to ONC18, ON Semiconductor’s 180 nm digital and mixed-signal technology platform.
    Single SLP macro densities ranging up to 256 kilobits (Kbits) will be available.
    "We chose Sidense's OTP intellectual property for its low power and small area and also because it doesn't require any changes or additions to our standard process flow."
    Sidense Corp. provides secure, very dense and reliable non-volatile, one-time programmable (OTP) memory IP for use in standard-logic CMOS processes with no additional masks or process steps required and no impact on product yield. The Company's innovative one-transistor 1T-Fuse™ architecture provides the industry's smallest footprint, most reliable and lowest power Logic Non-Volatile Memory (NVM) IP solution. With over 70 patents granted or pending, Sidense OTP provides a field-programmable alternative solution to Flash, mask ROM and eFuse in many OTP and MTP applications.

    The ONC18 process is an ideal platform for developing low power and highly integrated digital and mixed-signal application-specific integrated circuit (ASIC) devices for automotive, industrial and medical applications
    The ONC18-based solutions will be manufactured at ON Semiconductor's 8-inch wafer fabrication facility in Gresham, Oregon, so the process is also expected to prove attractive for designers of U.S. military applications seeking domestic production with ITAR-compliant partners
    ONC18 will allow designers in the automotive, industrial, medical and military sectors to develop integrated, low-power digital and mixed-signal ASICs quickly and cost-effectively
    The ?on-shore' nature of the fabrication will be particularly useful for US military customers, while planned developments for the process further underline ON Semiconductor's commitment to the custom foundry business
    Suitable for ASICs requiring up to 10 M gates, the ONC18 process features between four and six levels of metal and allows designers to integrate 1.8 volts (V) core voltage with 1.8 V and 3.3 V input/output (I/O)
    Components for mixed signal design include a variety of resistors and nominal [1.0 femtofarad per micron squared (fF/?m2)] and high value (2.0 fF/?m2) stackable metal-insulator-metal (MIM) capacitors
    This base process supports an extensive and modular 0.18 micron BCD, and high voltage roadmap
    ON Semiconductor's new process is supported with a design kit offering comprehensive core, I/O and memory libraries
    Gate densities and power consumptions for high density core and mixed signal core cells are 124 K gates/mm2 and 46 microwatt per megahertz per gate (?W/MHz/gate) and 120 K gates/mm2 and 28 ?W/MHz/gate, respectively
    Memory options include 1.1 M bit synchronous single port and 512K bit dual port SRAM and 1.1M bit high-density, low-leakage VIA-programmable ROM
    Future development for the ONC18 platform will enable ON Semiconductor to launch enhanced mixed signal capabilities and options for higher voltage handling
    The new process design methodology is compatible with common digital and analog/mixed signal CAD tools, including those from Cadence?, Synopsys? and Mentor Graphics?
    ON Semiconductor specialty services, such as advanced die stitching and shuttle services for prototyping, are also available for ONC18-based designs
    For more information, please contact Kirk Peterson at or visit

    I-Fuse™ is an innovative method to logically program One-Time Programmable (OTP) memory with “Electro-migration by accelerating wear-out of logic devices”. Unlike other Non-Volatile Memory (NVM) programming methods that use “oxide rupture” or “storing charges” techniques that require high voltage for programming, I-Fuse requires no charge pump. I-Fuse has 100x reliability, 10% cell size, and 10% of programming current compared to traditional fuse. I-Fuse is scalable from 700nm to 28nm and below.
    The AT4K8O180GN0AA is organized as a 4Kx8 OTP memory with parallel programming mode. This is a kind of non-volatile memory fabricated in 0.18um standard CMOS core logic process. The OTP can be widely used in chip ID, security key, memory redundancy, parameter trimming, configuration setting, feature selection, and PROM, etc.
    * Fully compatible with standard 0.18um CMOS core logic process
    * High capacity: 4Kx8 parallel mode
    * Low voltage: 1.8V read and 3.6V program ****Note 3.6V program
    * Pure logic, no additional masks or process steps

    And here are OnSemi's EEPROMs and FLASH ICs...

    23rd June 2011 - OnSemi FLASH produced on ONC18 line
    ON Semiconductor has released new EEPROM (Electrically Erasable Programmable Read-Only Memory) devices for the automotive, medical, and consumer markets. The EEPROM devices include the high density 512 kilobit (kb) CAT24C512 and 1 megabit (Mb) CAT24M01, which have a 1.8 volt (V) to 5.5 V supply voltage range. The CAT24C512 and CAT24M01 employ 256 byte and 128 byte page write buffers respectively. Both devices support Standard 100 kilohertz (kHz), Fast 400 kHz, and Fast-Plus 1 megahertz (MHz) serial I2C protocols. These devices are manufactured on a 0.18 micrometer (µm) low power CMOS process at the ON Semiconductor owned and operated Gresham, Oregon facility.
    All of the new EEPROM devices feature a 100 year data retention period and support for 1,000,000 program/erase cycles.

  • jmgjmg Posts: 14,950
    Cluso99 wrote: »
    A simple google search has turned up these...

    Yup, for their ASIC flows, shows there are choices in the OTP column, but not documented if their full custom flash can be included in ASIC, with no process impact.

  • Cluso99 wrote: »
    samuell wrote: »
    Internal ROM is a bad idea IMHO, especially if it is FLASH. It will degrade. I really prefer an external SPI flash and load the program to RAM, in the same fashion of the P1. If the EEPROM degrades, just replace it instead of the whole MCU. Otherwhise it is a waste of silicon. But I probably said that before.

    Also, I read that it won't fit in the die, nevertheless. I think the presence, or absence (hopefully) of ROM should be cleared once and for all.
    Are you aware that P1 has 32KB of ROM?

    ROM, OTP, EEPROM, FLASH and MRAM are all different. Some form of this must be in the P2 to be able to boot, even if this is only to read/load from an external chip.
    Sorry, I was thinking about EEPROM, and FLASH, that is a kind of EEPROM, yet a more specific technology. Yes, P1 has an internal ROM, but that won't degrade since it is not even writable to start with.
    jmg wrote: »
    samuell wrote: »
    Internal ROM is a bad idea IMHO, especially if it is FLASH...I really prefer an external SPI flash and load the program to RAM, in the same fashion of the P1.

    ROM and FLASH are not the same thing.
    Even with off chip flash you need SOME code running, to load that into RAM, thus even P1 has internal ROM (Which you claim is a bad idea?)
    There are OTP systems that do not use charge storage, so have no corresponding degrade mechanism.
    I know, but I was a bit lazy. OTP ROM does not degrade indeed, just like any other ROM that can't be reprogrammed and is not electrically, or photonically, erasable. As for EEPROM, I prefer it outside the chip. Perhaps, I can use a FRAM instead on my board.
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