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Who's Copying Who? — Parallax Forums

Who's Copying Who?

ercoerco Posts: 20,244
edited 2017-09-28 17:58 in General Discussion
Just saw this new D-Stick in the Oct SERVO issue. Looks a lot like the FLiP module, amirite? Is this the new form factor? http://store.melabs.com/prod/DSTICK/DS2.html

K40_stick_479w.jpg

Comments

  • And they do it wrong also, the better way would be header with long pins, so one would have pins on the bottom and a header on the top.

    Sad,

    Mike
  • kwinnkwinn Posts: 8,697
    msrobots wrote: »
    And they do it wrong also, the better way would be header with long pins, so one would have pins on the bottom and a header on the top.

    Sad,

    Mike

    I agree, but they do have a good reason for not using long header pins.

    Rounded machined pins are easy on spring contacts allowing for multiple insertion cycles

    I have had no success in finding long enough machined pins for a header on top and bottom pins long enough for a prototyping board or IC socket.
  • I dunno... The Cypress PSOC 4/5/6 line immediately comes to mind, and predates FLiP by several years.
  • GordonMcCombGordonMcComb Posts: 3,366
    edited 2017-09-28 23:08
    They've been doing these modules for quite some time. I think the first iterations go back maybe 7 or 8 years, possibly longer. Or were you talking about manufacturing style (board on headers), rather than general form factor?

    One of my first PIC experimenters boards came from ME Labs. I wasn't fond of PIC BASIC, but it's serviceable.

    As for the form factor of combining an MCU with all the other components for a stand-alone device, the original BS1 might be the forerunner of most of these. With the advent of USB and micro connectors, they have the PC port built into the module, which allows the module to be truly independent: apply power and go.

    I'd be interested if there was a mainstream (readily available commercially) composite module than the BS1. To fit the bill, it has to combine MCU, program memory, crystal or resonator, regulator, RS-232 interface, and other pieces. There may have been, but my attention wasn't going that direction in the early 1990s. I was still experimenting with Z80s!
  • GenetixGenetix Posts: 1,740
    edited 2017-09-28 23:52
    For a number of years in the 90's Kingston Technology had their TurboChip series of CPU upgrades for older systems.
    They were not in a DIP format but they were newer CPUs supported by clock and voltage translation circuitry.

    I think a few of the old 80's 6502 upgrades were in a DIP format.
    I also remember replacing the 8088 from an IBM PC with a V20 processor in the early 90's.
  • TorTor Posts: 2,010
    edited 2017-09-29 11:18
    Genetix wrote: »
    I think a few of the old 80's 6502 upgrades were in a DIP format.
    I also remember replacing the 8088 from an IBM PC with a V20 processor in the early 90's.
    Not sure what you mean about "6502 upgrades", but every 6502 and 65c02 were and are available in DIP packing. Including the 65c816. The original 6502 'real upgrade' chip (as in: Out with the old one, in with the new one, power on), the 65802, isn't sold anymore, but was of course DIP (DIP 40, same format as the D-stick in the first post) too.
    DIP is alive for lots of stuff (including Z80 etc). And the Parallax Propeller (P1), of course..

    (Hm, I have a V20 (and a V30 or two) somewhere.. no PC around to upgrade though.)

  • Heater.Heater. Posts: 21,230
    The V20 was great. It had a low power mode. Which meant it ended up in a portable, battery powered, wireless data communications project I worked on.

    That was great except the only way to wake it up from deep sleep was my poking it with an NMI. That meant that every possible source of interrupt had to go through the NMI and hence to the NMI handler. That handler then had to take care of all the interrupt source masking, interrupt priorities, nested interrupts etc. It became the most horrible, twisted, fragile, incomprehensible piece of assembler I have ever seen! It suffered no end of race conditions for a long time.

    Then, they wanted to build an Ada run time and it's scheduler on top of it, grrr....



  • Tor,

    It's been a long time so I may not remember correctly but I thought there were several drop in faster versions of the 6502. I think most were made for the Apple II.


    Heater,

    Aren't you glad that you don't need to bother with interrupts on the Propeller. That was genius on Chip's part.
  • Heater.Heater. Posts: 21,230
    I am indeed very glad we don't have to use interrupts on the Propeller. I have been singing the praises of that stroke of genius for years now.

    I was even campaigning against adding interrupts to the P2 design. Which it now has....

  • TorTor Posts: 2,010
    edited 2017-10-01 19:55
    Genetix,

    The first upgrade for the 6502 on the Apple II was the 65c02, but it was not a drop-in replacement. The Apple II had severe timing issues and some 65c02 (there were multiple sources) would work in a subset of machine models, others would not. There were some articles about it in Apple Assembly Line around the time, by Bob Sander-Cederlof. He keeps the magazines online somewhere btw.

    The 65c02 CPU became faster over the years (today's DIP versions are 14 MHz, but that's very conseratively rated - 25MHz is possible under normal conditions), but the Apple can't run faster than it's designed for. If you wanted faster it would require a co-processor extension as far as I remember (which could even be a Z80, to run CP/M)
  • Cluso99Cluso99 Posts: 18,066
    Didn't Apple use something like a 65816 in the GS?
  • TorTor Posts: 2,010
    edited 2017-10-02 05:27
    The 65802, a '16 with a 16-bit address bus. It's not in production anymore (unlike the 65c816), but you can still find a few sources on the net. But they're rare. Never seen one. Didn't buy a GS, but in hindsight I should have.
  • GenetixGenetix Posts: 1,740
    edited 2017-10-02 17:17
    Yes, Cluso, the Apple //gs used a 65816.

    Tor, I think you have them mixed up. The 802 is a 16-bit chip but uses an 8-bit bus while the 816 was 16-bit on a 16-bit bus.


    Heater, hopefully Chip has interrupts disabled by default.
  • Heater.Heater. Posts: 21,230
    Genetix,

    No idea. But as far as I understand interrupts in one COG can not influence the deterministic execution of any other COG. So all is good.

  • Cluso99Cluso99 Posts: 18,066
    Heater. wrote: »
    Genetix,

    No idea. But as far as I understand interrupts in one COG can not influence the deterministic execution of any other COG. So all is good.
    Not quite. One COG can interrupt another, providing the other has interrupts enabled.
  • TorTor Posts: 2,010
    Genetix,
    You're right, I mixed up a couple of my memory threads. The GS used the '16 of course. The 65802 was actually sold as an upgrade for the Apple II, for some time.
  • Heater.Heater. Posts: 21,230
    edited 2017-10-03 05:13
    It's very good that a COG can signal another COG with interrupts.

    In that case the programmer has given up deterministic execution in the same way as waiting on a pin or LOCK etc.

    All sounds good to me.
  • Cluso99Cluso99 Posts: 18,066
    Heater. wrote: »
    It's very good that a COG and signal another COG with interrupts.

    In that case the programmer has given up deterministic execution in the same way as waiting on a pin or LOCK etc.

    All sounds good to me.
    Yep. Best of both worlds :)

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