P2 PLLs - registers and emulation
jmg
Posts: 15,148
Right now, builds are not using even a fixed FPGA PLL, but the real P2 will use custom cells of [XtalOsc+bias resistor + Schmitt-buffer] and also [VCO and 3 x Dividers and PhaseCompare] to generate the system clock.
From other threads:
leads me to wonder
a) What Xtal range, and PLL control registers / dividers & PFD range are planned in final P2 ?
b) How much test coverage can those get, using a FPGA, given above caveats ?
An external PLL can be updated live at run-time, but modern parts like Si5351A have i2c bus control and rather complex register sets.
There are some older PLLs that have simpler regs and more direct parallel bus control like
OnSemi
NBC12430 :
fPD = 1MHz= Xi/16,
fVCO = 400−800 MHz,
Fo = fVCO/(1,2,4,8)
Feedback divider = 9b [200..400],
fVCO/2/(FBD)
IDT
ICS844S42I Xtal = 16MHz,
fPD = Xi/4 or Xi/2,
fVCO =1296 – 2592MHz
Fo = fVCO/(1,2,3,4,6,8,16)
Feedback divider = 10b [162..648],
Those (with some divider augmentation ) may allow P2 PLL register emulation in a FPGA, by using the external VCO/PLL devices.
Will that get close enough, or is it better to have a Si5351A, with an external MCU, or a Soft CPU in the fpga corner, ( or direct verilog) to convert the P2 PLL registers to i2c array mapping needed by Si5351A ?
The Si5351A is easily available and comes on a small Board. Good to 200MHz Fo.
https://www.adafruit.com/products/2045
Edit : SiLabs AN619 has info on register values.
Si5351A
Xtal = 25MHz, 27MHz
fVCO = 600 to 900 MHz
fO = fVCO/(R*M), R = 1, 2, 4, 8,....128 , M = 4, 6, 8..900 in integer mode.
fPD - unclear ? 10 to 40 MHz ?
CLkIn_Div = (1,2,4,8) for 10MHz~> 100MHz on extclk.
If it is kept in integer mode, maybe this can map-over to P2 PLL registers reasonably ?
From other threads:
Can the FPGA inbuilt PLL's be coupled to look like P2 PLLs' for run-time changes, and with the same quantisation ?. (ie register emulation)
Or, is the design limited to build-time PLL choices ?
If the PLL is working, can we modify the clock?
In my experience, to get an Altera PLL to feed from an NCO, the only way to do it is to output the NCO on a pin and then input it on another to feed the PLL. Quartus is very picky like that.
You can reconfigure PLLs at run-time, but you need to feed them a configuration bitstream. Not simple.
leads me to wonder
a) What Xtal range, and PLL control registers / dividers & PFD range are planned in final P2 ?
b) How much test coverage can those get, using a FPGA, given above caveats ?
An external PLL can be updated live at run-time, but modern parts like Si5351A have i2c bus control and rather complex register sets.
There are some older PLLs that have simpler regs and more direct parallel bus control like
OnSemi
NBC12430 :
fPD = 1MHz= Xi/16,
fVCO = 400−800 MHz,
Fo = fVCO/(1,2,4,8)
Feedback divider = 9b [200..400],
fVCO/2/(FBD)
IDT
ICS844S42I Xtal = 16MHz,
fPD = Xi/4 or Xi/2,
fVCO =1296 – 2592MHz
Fo = fVCO/(1,2,3,4,6,8,16)
Feedback divider = 10b [162..648],
Those (with some divider augmentation ) may allow P2 PLL register emulation in a FPGA, by using the external VCO/PLL devices.
Will that get close enough, or is it better to have a Si5351A, with an external MCU, or a Soft CPU in the fpga corner, ( or direct verilog) to convert the P2 PLL registers to i2c array mapping needed by Si5351A ?
The Si5351A is easily available and comes on a small Board. Good to 200MHz Fo.
https://www.adafruit.com/products/2045
Edit : SiLabs AN619 has info on register values.
Si5351A
Xtal = 25MHz, 27MHz
fVCO = 600 to 900 MHz
fO = fVCO/(R*M), R = 1, 2, 4, 8,....128 , M = 4, 6, 8..900 in integer mode.
fPD - unclear ? 10 to 40 MHz ?
CLkIn_Div = (1,2,4,8) for 10MHz~> 100MHz on extclk.
If it is kept in integer mode, maybe this can map-over to P2 PLL registers reasonably ?
Comments
It looks like testing the P2 PLL could be a challenge!