Prop2 FPGA files!!! - Updated 2 June 2018 - Final Version 32i

cgracey · September 2015

UPDATED 2 June 2018 - Final Version 32i

This is the 2nd v32i posted. It has a new Prop123-A7 file that hopefully fixes whatever was wrong with the first-posted one.

WHAT's NEW:

* ROM now includes SD booter and TAQOZ Forth
* Silicon speed will be rated at 180MHz

This Verilog has gone to OnSemi and is the tentative final version, unless a bug is discovered.

Please give these latest files a sanity check with your FPGA boards.

			  smart
	           cogs	  pins	RAM	Freq	CORDIC	Filename
	         +-----------------------------------------------------------------------------------------
Prop123-A9       |  16	   7	 1024k	80MHz	Yes	Prop123_A9_Prop2_16cogs_v32i.rbf	- not ready
Prop123-A9       |  8	  64	  512k	80MHz	Yes	Prop123_A9_Prop2_8cogs_v32i.rbf **	- READY
BeMicro-A9       |  16	   7	 1024k	80MHz	Yes	BeMicro_A9_Prop2_16cogs_v32i.jic *	- not ready
BeMicro-A9       |  8	  64	  512k	80MHz	Yes	BeMicro_A9_Prop2_8cogs_v32i.jic */**	- READY
Prop123-A7       |  4	  38	  512k	80MHz	Yes	Prop123_A7_Prop2_v32i.rbf		- READY
DE2-115          |  4	  20	  256k	80MHz	Yes	DE2_115_Prop2_v32i.pof *		- READY
BeMicro-A2       |  1	   7	  128k	80MHz	No	BeMicro_A2_Prop2_v32i.jic *		- READY
DE0-Nano         |  1	   8	   32k	80MHz	No	DE0_Nano_Prop2_v32i.jic			- READY
DE0-Nano Bare    |  1	   8	   32k	80MHz	No	DE0_Nano_Bare_Prop2_v32i.jic		- READY

*  These images always map SD card pins {CSn,CLK,DO,DI} into P[61:58].
** These images represent the logic and memory that will be built in silicon.

DOCUMENTATION:

https://docs.google.com/document/d/1UnelI6fpVPHFISQ9vpLzOVa8oUghxpI6UpkXVsYgBEQ/edit?usp=sharing

https://docs.google.com/spreadsheets/d/1usUcCCQVp3liAqENX9rvX-XVqJomMREhKYExM_taG0A/edit?usp=sharing

NEWEST ZIP FILE:

https://drive.google.com/file/d/1huxRvHmr07ItoO06rLYGsOKmMQVEOA4R/view?usp=sharing

Older news:

* BUG FIX from v32a - SETQ+WRLONG was writing incorrect 2nd long if prior SETQ2+RDLONG/WRLONG
* BUG FIX from v32a - SETQ2+WRLONG was writing incorrect 2nd long if prior SETQ+RDLONG/WRLONG
* Debug system greatly improved with common-sense breakpoint behavior, individual cog enables, 8-long ROM in cogs to facilitate entry/exit, more breakpoint conditions and status data.
* LOCKs improved to retire if owner cog stops, LOCKSET/LOCKCLR changed to LOCKTRY/LOCKREL. See "lock_test.spin2"
* XBYTE improved with total control in only 9 bits via _RET_+SETQ. Added collapsible groups of 16 bytecodes that use a single LUT entry.
* RDFAST/WRFAST now exit in two clocks if D[31] set.
* WAITX with WC/WZ now waits 2 + (D & RND) clocks. For example, 'WAITX #$F WZ' randomly waits 2 + 0..15 clocks. Great for adding test jitter.
* XORO32 algorithm improved
* Smart pin timing cleaned up around enabling/disabling smart modes to eliminate glitches.
* Streamer pins now wrap around for 16-and 32-bit data paths on upper 8-pin offsets
* New CRCBIT/CRCNIB instructions compute up to 32-bit CRC's, 1 or 4 bits at a time.
* Latent hubexec bug fixed with hub instructions CLKSET/COGxxxx/LOCKxxx and CORDICs.
* DJS/DJNS have been replaced by DJF/DJNF which check for $FFFF_FFFF instead of MSB set.
* PTRA/PTRB are now 32-bit (they were 20-bit).
* The hardware stack is now 32-bit (it was 22-bit).
* {SETQ+}COGINIT data paths are now 32-bit (they were 20-bit).
* C/Z flag reporting for ENCOD and ONES has been fixed (C/Z were swapped).
* ENCOD now sets C if S>0 (encode operation was valid).
* New test overflow and branch instruction: TJV.
* SUMxx instructions now report 'correct sign' into C for TJV compatibility.
* New 'ONES D,S' instruction gets number of '1's in S into D.
* More data reported in GETINT and SETBRK. See documentation.
* Last 16KB of hub RAM also appears at $FC000..$FFFFF and is write-protectable. See documentation.
* XORO32 PRNG quality improved 16x with help from PractRand author, Evanh, and TonyB_.
* 16KB ROM now reads 8x faster into hub RAM during boot, loads into last 16KB of RAM.
* Last 16KB of RAM now always maps to $FC000..$FFFFF and can be write-protected.
* GETXACC gets snapshot of Goertzel sums into D and next S, replaces GETXCOS/GETXSIN.
* BeMicro-A2, BeMicro-A9, and DE2-115 boards can now have their SD card pins mapped into P[61:58].
* All pin inputs are now registered, which seems to have eliminated intermittent problems.
* Reset timer has been reduced from 50ms to 3ms to match silicon.
* Smart pin asynchronous serial transmitter now drives the stop bit for its duration.
* New smart pin timeout/watchdog modes
* Simpler loader protocol, PNut.exe downloads much quicker.
* XORO32 now iterates D and puts PRNG result into next instruction's S.
* Hub instruction timing has been scaled to the number of cogs to speed things up and save logic.
* Debug ISR instructions have been moved from $FFFC0..$FFFFC to $FFFFC-downwards
* Speed changed back to 80MHz for reliability.
* ADDS/ADDSX/SUBS/SUBSX now report signed carry/borrow into C, instead of signed overflow
* Streamer NCO rollover event no longer stays "on" when streamer commands run out
* SKIP/SKIPF/EXECF/XBYTE now allow CALLs in skip sequences, as well as interrupts
* XBYTE optionally writes C/Z with bytecode index[1:0]
* Pin filtering improved with selectable CT[31:0] tap and 2/3/5/8-sample unanimity
* New RFVAR/RFVARS variable-length, two-clock, unsigned/signed data reading, 1..4 bytes
* TESTB/TESTBN and TESTP/TESTPN (were TESTIN/TESTNIN) now have flag AND/OR/XOR
* XORO32 instruction to iterate xoroshiro32+ long for high-quality repeatable PRNG
* XBYTE now has LSB/MSB-bias selection based on '_RET_ SETQ {#}D' LSB
* 120MHz top speed - your code starts at 60MHZ, use 'CLKSET #$FF' to switch to 120MHz
* New custom bytecode executor with 6-clock overhead (see xbyte.spin2 in zip file)
* SKIPF now behaves like SKIP during hub-exec
* PRNG upgraded to Xoroshiro128+ (accessed via GETRND, was 32-bit LFSR)
* New _RET_ instruction prefix for automatic RETurn, adds 2 clocks in cog exec mode.
* New SKIP/SKIPF instructions for bitmask-based instruction skipping.
* New EXECF instruction for branching plus fast skipping in cog memory.
* Additional ALTxx instructions for reading and writing nibbles, bytes, and words within cog registers.
* Single-stepping/interrupts around REP blocks made consistent between cog and hub execution modes
* 'FLTxx D/#' instructions clear DIR bit and affect OUT bit, read IN bit into C
* 'DRVxx D/#' instructions set DIR bit and affect OUT bit, read IN bit into C
* 2-clock RDPIN/WRPIN/WXPIN/WYPIN with automatic acknowledge
* 2-clock RQPIN ('read quiet') like RDPIN without acknowledge, allows concurrent reading
* Improved booter ROM now runs at 2M baud, thanks to Jmg's ongoing efforts
* ALTB added to facilitate accessing multi-register bit fields (SETBYTS removed)
* Event jumps added: JINT/JNINT/JCT1/JNCT1...
* SETPEQ/SETPNE replaced with SETPAT, C flag picks INA/INB, Z flags picks equal/not-equal
* Improved booter ROM, now supports 3-pin SPI and half-duplex serial
* ADRA/ADRB renamed to PA/PB
* New 'CALLPA/CALLPB D/#,S/#' instructions write D/# to PA/PB and call S/#
* 4 selectable events for pins, locks, and LUT r/w's
* Direct pin DIR instructions: DIRL/DIRH/DIRC/DIRNC/DIRZ/DIRNZ/DIRN D/#
* Direct pin OUT instructions: OUTL/OUTH/OUTC/OUTNC/OUTZ/OUTNZ/OUTN D/#
* Direct pin IN instructions: TESTIN/TESTNIN D/#
* Increment-test jumps: IJZ/IJNZ/IJS/IJNS D,S/#rel9
* Interrupt-triggering instructions: TRGINT1/TRGINT2/TRGINT3
* Support for Prop123-A7 boards added after Tubular fixed PLL problem
* Support for the BeMicro CV A9 board was added
* Hub/eggbeater can now be 16, 8, 4, 2, or 1 slice of cog and hub RAM
* Fewer slices means lower latency
* Cogs' FIFO's are reduced to match slices now, saving logic
* FPGA images are optimized for their number of slices (not all 16, anymore)
* The Verilog source code is now capable of making any sub-version of Prop2

Older zip files:

https://drive.google.com/file/d/1HR-FidARFY4fMPyuWs2ZX_qMOZZEnJAA/view?usp=sharing
https://drive.google.com/file/d/1f6CgxNcDYhltlyu_oi9DWVdfh7DSrsQz/view?usp=sharing
https://drive.google.com/file/d/1jVTct_65-axldhWMKmwPjCRacNJ2_cTh/view?usp=sharing
https://drive.google.com/file/d/1znnWppXrkmgJWZ2Q5OAfjip7R-ocXpV-/view?usp=sharing
https://drive.google.com/file/d/1chbWDzbchfSR-LMJwzE0MUNNFU7iIWMk/view?usp=sharing
https://drive.google.com/file/d/1s1qedgO9WWM8Du1LSEJnJc7Iq0r0hjub/view?usp=sharing
https://drive.google.com/file/d/1PSl-OZWxA2mqkmJrRp9JIaDHZmNxGgDW/view?usp=sharing
https://drive.google.com/file/d/1gphMOGE7VFPKCth8dWEQzXaS1syv1vLZ/view?usp=sharing
https://drive.google.com/file/d/19DSzQEL8lRGjxMxUVH0ZVv8GOvigR3Db/view?usp=sharing
https://drive.google.com/file/d/15X8UxpwyIxHmfdEYVi5E99DJSaHZtUaC/view?usp=sharing
https://drive.google.com/file/d/0B9NbgkdrupkHSGlQT3ZGZTN0UTA/view?usp=sharing
https://drive.google.com/file/d/0B9NbgkdrupkHaW1YM1JjSEpESnM/view?usp=sharing
https://drive.google.com/file/d/0B9NbgkdrupkHQ3g2MHhkbE8xeVU/view?usp=sharing
https://drive.google.com/file/d/0B9NbgkdrupkHb3pUTTZmaC1TWlU/view?usp=sharing
https://drive.google.com/file/d/0B9NbgkdrupkHcGNrd3V1Q0hyZnc/view?usp=sharing
https://drive.google.com/file/d/0B9NbgkdrupkHYXhyWkxvMkNrSDQ/view?usp=sharing
https://drive.google.com/file/d/0B9NbgkdrupkHcmk4cWV0dkgxOHM/view?usp=sharing
https://drive.google.com/file/d/0B9NbgkdrupkHdjMxaXRkaWlxR3M/view?usp=sharing
https://drive.google.com/file/d/0B9NbgkdrupkHWVNTY2pSNHRxUkE/view?usp=sharing
https://drive.google.com/file/d/0B9NbgkdrupkHMlVrUjRLd2c5SlE/view?usp=sharing
https://drive.google.com/file/d/0B9NbgkdrupkHRnRtMDFRS0RDOXM/view?usp=sharing
https://drive.google.com/file/d/0B9NbgkdrupkHQkVvaXU1QmVxNXc/view?usp=sharing
https://drive.google.com/file/d/0B9NbgkdrupkHa0hFa01CamZNMms/view?usp=sharing
https://drive.google.com/open?id=0B9NbgkdrupkHRUwxSER4Q3ZXOE0
https://drive.google.com/file/d/0B9NbgkdrupkHMmRKNzNpLW5BdTg/view?usp=sharing
https://drive.google.com/file/d/0B9NbgkdrupkHRWswaUdaS1g0SjQ/view?usp=sharing
https://drive.google.com/file/d/0B9NbgkdrupkHUVZOdE5WLS1vaEE/view?usp=sharing
https://drive.google.com/file/d/0B9NbgkdrupkHMDBEejlldDh6eTQ/view?usp=sharing
https://drive.google.com/file/d/0B9NbgkdrupkHWnJobU5oajVoYUU/view?usp=sharing
https://drive.google.com/a/parallax.com/file/d/0B9NbgkdrupkHVklDQ0J5TzZpRVE/view?usp=sharing
https://drive.google.com/a/parallax.com/file/d/0B9NbgkdrupkHN0t6NjFFZnNnOWc/view?usp=sharing
https://drive.google.com/file/d/0B9NbgkdrupkHSThLdkFVZVA3ZWc/view?usp=sharing
https://drive.google.com/file/d/0B9NbgkdrupkHRTlOUWVWMXBJYU0/view?usp=sharing
https://drive.google.com/file/d/0B9NbgkdrupkHUlZjWkI4ZlRLQVk/view?usp=sharing
https://drive.google.com/open?id=0B9NbgkdrupkHRTFfeG9POU42YzA
https://drive.google.com/file/d/0B9NbgkdrupkHZi01dWdDdWZ2VTA/view?usp=sharing
https://drive.google.com/file/d/0B9NbgkdrupkHS0dPbDkwZVRneXM/view?usp=sharing
https://drive.google.com/open?id=0B9NbgkdrupkHS0tacW5wNndFb0U
https://drive.google.com/open?id=0B9NbgkdrupkHNE1NdVNaSWFKbEk
https://drive.google.com/open?id=0B9NbgkdrupkHN2E1bkk2YW5tZGs
https://drive.google.com/open?id=0B9NbgkdrupkHV3h0dTV2ZGZmVkk
https://drive.google.com/open?id=0B9NbgkdrupkHbTZ2U2ZNN1gzRVk
https://drive.google.com/open?id=0B9NbgkdrupkHVDA2Vm5hN1FwaTA
https://drive.google.com/open?id=0B9NbgkdrupkHZE1FMDNnUVJydlU
https://drive.google.com/open?id=0B9NbgkdrupkHWW94bW5HLXc2N0E
https://drive.google.com/open?id=0B9NbgkdrupkHbkliR0YtZGFUbE0
https://drive.google.com/file/d/0B9NbgkdrupkHSEhHOFROWk52cXc/view?usp=sharing
https://drive.google.com/file/d/0B9NbgkdrupkHR2dBcjZYZEpnWlE/view?usp=sharing

David Betz · September 2015

Thanks Chip!

cgracey · September 2015

David Betz wrote: »

Thanks Chip!

I trust you have that add-on board we made?

ozpropdev · September 2015

Thanks Chip!

David Betz · September 2015

cgracey wrote: »

David Betz wrote: »

Thanks Chip!

I trust you have that add-on board we made?

Yes, I have the original DE2-115 add-on board. I don't have the revised one that was released more recently. Is the original one okay?

cgracey · September 2015

David Betz wrote: »

cgracey wrote: »

David Betz wrote: »

Thanks Chip!

I trust you have that add-on board we made?

Yes, I have the original DE2-115 add-on board. I don't have the revised one that was released more recently. Is the original one okay?

If it looks like this:

ozpropdev · September 2015

Chip
P2 loaded into Prop123-A7 Ok.
16 cog leds program blinks ok.
No DAC output from sin_cos_dacs.spin?

What are your dac clock pin assignments?

David Betz · September 2015

That's the one I have. I think there is a newer version with mounting holes on either side of the header. I just powered up my DE2-115 board and it is still running the most recent P2-hot image so I guess everything is working. I get a monitor prompt. I'm now downloading Quartus so I can program the new FPGA image. Thanks!!

Baggers · September 2015

Thanks Chip, I'll have a play now, and let you know how it goes.

cgracey · September 2015

ozpropdev wrote: »

Chip
P2 loaded into Prop123-A7 Ok.
16 cog leds program blinks ok.
No DAC output from sin_cos_dacs.spin?
What are your dac clock pin assignments?

I just poked my scope into the upper VGA pin receptacles. It's outputting on Dac0 Green and Blue.

cgracey · September 2015

Baggers wrote: »

Thanks Chip, I'll have a play now, and let you know how it goes.

Thanks. Without doc's, it's kind of an adventure game.

Baggers · September 2015

All the more fun

cgracey · September 2015

It's neat to think how in the blink program, every cog is running in hub-exec simultaneously. That egg beater is going to town. All this time, I've just been doing one-cog compiles for testing. I've never seen it all work together, until tonight.

ozpropdev · September 2015

Ok, confirm dac0 green and dac0 blue working.
cooment in code tricked me

'Goertzel mode, output sin/cos on dacs 1/0

Scope was connected to Dac0 red and dac1 red
Schematic refers to dac0 and dac1, pcb overlay refers to dac0 to 5.

cgracey · September 2015

ozpropdev wrote: »
Ok, confirm dac0 green and dac0 blue working.
cooment in code tricked me
'Goertzel mode, output sin/cos on dacs 1/0
Scope was connected to Dac0 red and dac1 red
Schematic refers to dac0 and dac1, pcb overlay refers to dac0 to 5.

We are swapping those signals around on the A9 board so it makes sense. Sorry about that. You might have heard about Mixed-up Signal Processing.

Peter Jakacki · September 2015

Thanks Chip, I am dusting off my DE2-115 and the add-on and see how it goes

David Betz · September 2015

I hate to admit it but I seem to have lost the instructions for programming an image into the DE2-115 board. I have the programmer downloaded but I'm not sure how to configure it to program Chip's image. Can anyone give me instructions?

ozpropdev · September 2015

David
On DE2-115 set switch on left side to program

In Quartus programmer
Mode - Active serial programming
Open file DE2_115_prop2.pof
Check pconfigure
Press start

P.S.: USB cable connected to USB Blaster port top left corner of DE2-115.
Prop plug on adapter board (logo facing away from you)

David Betz · September 2015

ozpropdev wrote: »

David
On DE2-115 set switch on left side to program

In Quartus programmer
Mode - Active serial programming
Open file DE2-115_prop2.pof
Check pconfigure
Press start

Thanks! I made the mistake of trying to use JTAG mode and "Find Device". That doesn't work. :-)

David Betz · September 2015

Ugh. Now I can't use PNut.exe to load a program because my PropPlug got assigned COM24.

David Betz · September 2015

David Betz wrote: »

Ugh. Now I can't use PNut.exe to load a program because my PropPlug got assigned COM24.

Never mind. I went into the device manager and reassigned it to COM2 and I now have 9 LEDs blinking! I assume that means that there are 9 COGs implemented on the DE2-115?

VonSzarvas · September 2015

Could you go into windows device manager, show hidden items, then delete one of the com ports thats not being used, but allocated to one of the lower port numbers?

ozpropdev · September 2015

David Betz wrote: »

David Betz wrote: »

Ugh. Now I can't use PNut.exe to load a program because my PropPlug got assigned COM24.

Never mind. I went into the device manager and reassigned it to COM2 and I now have 9 LEDs blinking! I assume that means that there are 9 COGs implemented on the DE2-115?

Press Ctrl-G to "Get Hardware Version"

David Betz · September 2015

ozpropdev wrote: »

David Betz wrote: »

David Betz wrote: »

Ugh. Now I can't use PNut.exe to load a program because my PropPlug got assigned COM24.

Never mind. I went into the device manager and reassigned it to COM2 and I now have 9 LEDs blinking! I assume that means that there are 9 COGs implemented on the DE2-115?

Press Ctrl-G to "Get Hardware Version"

I just noticed that before I read your message. Very nice! Now, does anyone have a serial driver that will work with this image?

Rayman · September 2015

Guess it's time to unbox my Parallax DE2-115 board... Got it that April 1 when P2 was too hot and wasn't a joke... Been sitting in unopened box since...

Thanks for the screen shots, answers a question about what we get with DE2-115...
Looks like 9 of 16 cogs (as mentioned) and 256 of 512 kB.

mindrobots · September 2015

Hey! It's Saturday morning, here in the States, don't any of you guys have chores to do? Errands to run? Honey-do's to do? Kids to tote to soccer? Wives to appease?

...at least I can dream of P2 a bit more while I chore my way around the house.

David Betz · September 2015

mindrobots wrote: »

Hey! It's Saturday morning, here in the States, don't any of you guys have chores to do? Errands to run? Honey-do's to do? Kids to tote to soccer? Wives to appease?

...at least I can dream of P2 a bit more while I chore my way around the house.

You're right! Time to head to the dump...

Kerry S · September 2015

Great job Chip!

Rayman · September 2015

I think I almost understand the blinky example, but some things look magic...

What does "orgh 1" do? Why not just orgh ? Does this code start at $1000 (I think so)?

The last two lines with org and res x are hurting my brain...
Does the compiler load anything after "org" into cog before starting?
Or does this only work for "res" reserved space that doesn't need initializing?

Rayman · September 2015

I think I see both Parallax DE2-115 add on boards and the FPGA123 board have a 40-pin header for access to P2 digital I/O.
Unfortunately, they are wired differently.

Looks like the DE2-115 board with give me P0..P28 with 3.3 V I/O on 40-pin header.
FPGA123 appears to give P0-P31 with 3.3 V I/O on 40-pin header.

Do I have this right?

Baggers · September 2015

After getting DE2 out, visitors came, they've now gone and I've got it booted up and LEDs flashing!

Time to play!

Thanks Chip

Equip your Genius

Categories

Prop2 FPGA files!!! - Updated 2 June 2018 - Final Version 32i

Comments