New 16-Cog, 512KB: Instruction List plus Semantics & Naming discussion
Cluso99
Posts: 18,069
Here is the latest instruction set posted by Chip ~9 Apr 2014
I will try and keep this updated until the next FPGA code release.
I have proposed a few changes in the posts below that may simplify things, make the manual easier to write, and reduce the perceived number of instructions.
And here is the instructions grouped, together with comments and flag settings (some need to be added/corrected)
I will try and keep this updated until the next FPGA code release.
I have proposed a few changes in the posts below that may simplify things, make the manual easier to write, and reduce the perceived number of instructions.
Propeller P16X512x Instructions as of 2014/04/10 ------------------------------------------------------------------------------------------------------------------- ZCxS Opcode ZC I Cond Dest Source Instr00 01 10 11 Operand(s) Flags ------------------------------------------------------------------------------------------------------------------- ZCWS 00000ff ZC 1 CCCC DDDDDDDDD SSSSSSSSS RDBYTE RDBYTEC RDWORD RDWORDC D,PTRA/PTRB ZC ZC ZC ZC ZCWS 00001ff ZC 1 CCCC DDDDDDDDD SSSSSSSSS RDLONG RDLONGC RDQUAD SYSOP D,PTRA/PTRB ||| D,# ZC ZC ZC ZC ZCMS 00010ff ZC I CCCC DDDDDDDDD SSSSSSSSS ISOB NOTB CLRB SETB D,S/# ZC ZC ZC ZC ZCMS 00011ff ZC I CCCC DDDDDDDDD SSSSSSSSS SETBC SETBNC SETBZ SETBNZ D,S/# ZC ZC ZC ZC ZCMS 00100ff ZC I CCCC DDDDDDDDD SSSSSSSSS ROR ROL SHR SHL D,S/# ZC ZC ZC ZC ZCMS 00101ff ZC I CCCC DDDDDDDDD SSSSSSSSS RCR RCL SAR REV D,S/# ZC ZC ZC ZC ZCMS 00110ff ZC I CCCC DDDDDDDDD SSSSSSSSS ANDN AND OR XOR D,S/# ZC ZC ZC ZC ZCMS 00111ff ZC I CCCC DDDDDDDDD SSSSSSSSS MUXC MUXNC MUXZ MUXNZ D,S/# ZC ZC ZC ZC ZCMS 01000ff ZC I CCCC DDDDDDDDD SSSSSSSSS ADD SUB ADDX SUBX D,S/# ZC ZC ZC ZC ZCMS 01001ff ZC I CCCC DDDDDDDDD SSSSSSSSS SUMC SUMNC SUMZ SUMNZ D,S/# ZC ZC ZC ZC ZCWS 01010ff ZC I CCCC DDDDDDDDD SSSSSSSSS MOV NOT ABS NEG D,S/# ZC ZC ZC ZC ZCWS 01011ff ZC I CCCC DDDDDDDDD SSSSSSSSS NEGC NEGNC NEGZ NEGNZ D,S/# ZC ZC ZC ZC ZCMS 01100ff ZC I CCCC DDDDDDDDD SSSSSSSSS SETS SETD SETCOND SETINST D,S/# ZC ZC ZC ZC ZCMS 01101ff ZC I CCCC DDDDDDDDD SSSSSSSSS MIN MAX MINS MAXS D,S/# ZC ZC ZC ZC ZCMS 01110ff ZC I CCCC DDDDDDDDD SSSSSSSSS MUL MULS JMPSW TOPBIT D,S/# || D,S/@ | D,S/# ZC ZC ZC ZC ZCWS 01111ff ZC I CCCC DDDDDDDDD SSSSSSSSS DECOD5 ESWAP8 SPLITW MERGEW D,S/# ZC ZC ZC ZC ZCRS 10000ff ZC I CCCC DDDDDDDDD SSSSSSSSS TESTB TESTN TEST CMP D,S/# ZC ZC ZC ZC ZCRS 10001ff ZC I CCCC DDDDDDDDD SSSSSSSSS CMPX CMPS CMPSX CMPR D,S/# ZC ZC ZC ZC ZCMS 10010ff ZC I CCCC DDDDDDDDD SSSSSSSSS INCMOD DECMOD CMPSUB SUBR D,S/# ZC ZC ZC ZC ZCWS 10011ff ZC I CCCC DDDDDDDDD SSSSSSSSS MSGINA MSGINB ROLNIB ROLBYTE D,S/# ZC ZC ZC ZC ZCMS 10010ff ZC I CCCC DDDDDDDDD SSSSSSSSS DJZ DJNZ TJZ TJNZ D,S/@ ZC ZC ZC ZC ZCMS 10011ff ZC I CCCC DDDDDDDDD SSSSSSSSS WAITCNT D,S/# ZC ------------------------------------------------------------------------------------------------------------------- --WS 1010xnn nf I CCCC DDDDDDDDD SSSSSSSSS GETNIB SETNIB D,S/#,#0..7 -- -- --WS 1011xxn nf I CCCC DDDDDDDDD SSSSSSSSS GETBYTE SETBYTE D,S/#,#0..3 -- -- --LS 1100000 fL 1 CCCC DDDDDDDDD SSSSSSSSS WRBYTE WRWORD D/#,PTRA/PTRB -- -- --LS 1100001 fL 1 CCCC DDDDDDDDD SSSSSSSSS WRLONG WRQUAD D/#,PTRA/PTRB [s]| D/#,S/#[/s] -- -- --LS 1100010 fL I CCCC DDDDDDDDD SSSSSSSSS WAITPAE WAITPAN D/#,S/# -- -- --LS 1100011 fL I CCCC DDDDDDDDD SSSSSSSSS WAITPBE WAITPBN D/#,S/# -- -- --LS 1100100 fL I CCCC DDDDDDDDD SSSSSSSSS MSGDIRA MSGDIRB D/#,S/# -- -- --LS 1100101 fL I CCCC DDDDDDDDD SSSSSSSSS MSGOUTA MSGOUTB D/#,S/# [s]| D/#,S/@[/s] -- -- --LS 1100110 fL I CCCC DDDDDDDDD SSSSSSSSS JP [s]JPD [/s] D/#,S/@ -- -- --LS 1100111 fL I CCCC DDDDDDDDD SSSSSSSSS JNP [s]JNPD [/s] D/#,S/@ [s]| D/#,S/#[/s] -- -- --LS 1101000 fL I CCCC DDDDDDDDD SSSSSSSSS SETINDS ADJINDS D/#,S/# -- -- --LS 1101001 fL I CCCC DDDDDDDDD SSSSSSSSS WAITVID REP D/#,S/# | #23bits -- -- ------------------------------------------------------------------------------------------------------------------- ---- 11100xx x0 n nnnn nnnnnnnnn nnnnnnnnn AUGS AUGD <AUGS> <AUGD> #23bits -- -- -- -- ------------------------------------------------------------------------------------------------------------------- ---- 11101xx 00 0 CCCC fnnnnnnnn nnnnnnnnn JMP JMP #abs | @rel -- -- ---- 11101xx 00 1 CCCC fnnnnnnnn nnnnnnnnn CALL CALL #abs | @rel -- -- ---- 11101xx 01 0 CCCC fnnnnnnnn nnnnnnnnn CALLA CALLA #abs | @rel -- -- ---- 11101xx 01 1 CCCC fnnnnnnnn nnnnnnnnn CALLB CALLB #abs | @rel -- -- ---- 11101xx 10 0 CCCC fnnnnnnnn nnnnnnnnn LINK LINK #abs | @rel -- -- ---- 11101xx 10 1 CCCC fnnnnnnnn nnnnnnnnn LOCINST LOCINST #abs | @rel -- -- ---- 11101xx 11 0 CCCC fnnnnnnnn nnnnnnnnn LOCPTRA LOCPTRA #abs | @rel -- -- ---- 11101xx 11 1 CCCC fnnnnnnnn nnnnnnnnn LOCPTRB LOCPTRB #abs | @rel -- -- ------------------------------------------------------------------------------------------------------------------- --L- 1111xxx 00 L CCCC DDDDDDDDD xxx0000ff OFFP NOTP CLRP SETP D/# -- -- -- -- --L- 1111xxx 00 L CCCC DDDDDDDDD xxx0001ff SETPC SETPNC SETPZ SETPNZ D/# -- -- -- -- ZCL- 1111xxx ZC L CCCC DDDDDDDDD xxx0010ff GETP GETNP WAITPR WAITPF D/# ZC ZC -- -- --L- 1111xxx 00 L CCCC DDDDDDDDD xxx0011ff WAITPX SETTASK SETPTRA SETPTRB D/# -- -- -- -- --L- 1111xxx 00 L CCCC DDDDDDDDD xxx0100ff SETINDA SETINDB ADJINDA ADJINDB D/# -- -- -- -- --L- 1111xxx 00 L CCCC DDDDDDDDD xxx0101ff JMPT0 JMPT1 JMPT2 JMPT3 D/# -- -- -- -- --L- 1111xxx 00 L CCCC DDDDDDDDD xxx0110ff WAIT SETVID PUSH D/# -- -- -- Z-W- 1111xxx Z0 0 CCCC DDDDDDDDD xxx1000ff GETPTRA GETPTRB POP D Z- Z- Z- --R- 1111xxx 00 0 CCCC DDDDDDDDD xxx1100ff LOCPTRA LOCPTRB JMP CALL D -- -- ZC ZC --R- 1111xxx ZC 0 CCCC DDDDDDDDD xxx1101ff CALLA CALLB LINK D ZC ZC ZC ZC-- 1111xxx ZC 0 CCCC xxxxxxxxx xxx1110ff RET <RET> RETA RETB ZC ZC ZC ZC ---- 1111xxx 00 0 CCCC xxxxxxxxx xxx1111ff DCACHEX ICACHEX <empty> <empty> -- -- -- -- -------------------------------------------------------------------------------------------------------------------
And here is the instructions grouped, together with comments and flag settings (some need to be added/corrected)
--------------------------------------------------------------------------------------------------------------------------------- -----Z----- -----C-----
ZCWS 0000000 ZC 1 CCCC DDDDDDDDD SSSSSSSSS RDBYTE D,PTRA/PTRB Read into cog D(0-extended) from hub byte S[19..0] Result=0 n/a
ZCWS 0000001 ZC 1 CCCC DDDDDDDDD SSSSSSSSS RDBYTEC D,PTRA/PTRB Read into cog D(0-extended) from Cache or hub byte S[19..0] Result=1 n/a
ZCWS 0000010 ZC 1 CCCC DDDDDDDDD SSSSSSSSS RDWORD D,PTRA/PTRB Read into cog D(0-extended) from hub word S[19..1] Result=2 n/a
ZCWS 0000011 ZC 1 CCCC DDDDDDDDD SSSSSSSSS RDWORDC D,PTRA/PTRB Read into cog D(0-extended) from Cache or hub word S[19..1] Result=3 n/a
ZCWS 0000100 ZC 1 CCCC DDDDDDDDD SSSSSSSSS RDLONG D,PTRA/PTRB Read into cog D from hub long S[19..2] Result=4 n/a
ZCWS 0000101 ZC 1 CCCC DDDDDDDDD SSSSSSSSS RDLONGC D,PTRA/PTRB Read into cog D from Cache or hub long S[19..2] Result=5 n/a
ZCWS 0000110 ZC 1 CCCC DDDDDDDDD SSSSSSSSS RDQUAD D,PTRA/PTRB Read into cogs 4 x D from hub Quad S[19..4] Result=6 n/a
--LS 1100000 0L 1 CCCC DDDDDDDDD SSSSSSSSS WRBYTE D/#,PTRA/PTRB Write from cog D[7..0] to hub byte S[17..0] n/a n/a
--LS 1100000 1L 1 CCCC DDDDDDDDD SSSSSSSSS WRWORD D/#,PTRA/PTRB Write from cog D[15..0] to hub word S[17..1],0 n/a n/a
--LS 1100001 0L 1 CCCC DDDDDDDDD SSSSSSSSS WRLONG D/#,PTRA/PTRB Write from cog D[31..0] to hub long S[17..2],00 n/a n/a
--LS 1100001 1L 1 CCCC DDDDDDDDD SSSSSSSSS WRQUAD D/#,PTRA/PTRB Write quad cog D[31..0] to hub quad S[17..4],0000 n/a n/a
---- 1111xxx 00 0 CCCC xxxxxxxxx xxx111100 DCACHEX Invalidate Data Cache
---- 1111xxx 00 0 CCCC xxxxxxxxx xxx111101 ICACHEX Invalidate Instruction Cache
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------
ZCMS 0010000 ZC I CCCC DDDDDDDDD SSSSSSSSS ROR D,S/# Rotate D right by S[4..0] bits Result=0 D[0]
ZCMS 0010001 ZC I CCCC DDDDDDDDD SSSSSSSSS ROL D,S/# Rotate D left by S[4..0] bits Result=0 D[31]
ZCMS 0010010 ZC I CCCC DDDDDDDDD SSSSSSSSS SHR D,S/# Shift D right by S[4..0] bits Result=0 D[0]
ZCMS 0010011 ZC I CCCC DDDDDDDDD SSSSSSSSS SHL D,S/# Shift D left by S[4..0] bits Result=0 D[31]
ZCMS 0010100 ZC I CCCC DDDDDDDDD SSSSSSSSS RCR D,S/# Rotate carry right into D by S[4..0] bits Result=0 D[0]
ZCMS 0010101 ZC I CCCC DDDDDDDDD SSSSSSSSS RCL D,S/# Rotate carry left into D by S[4..0] bits Result=0 D[31]
ZCMS 0010110 ZC I CCCC DDDDDDDDD SSSSSSSSS SAR D,S/# Shift D arithemtically right by S[4..0] bits Result=0 D[0]
ZCMS 0010111 ZC I CCCC DDDDDDDDD SSSSSSSSS REV D,S/# Reverse 32-S[4..0] bottom bits in D and 0-extend Result=0 D[0]
ZCMS 0011000 ZC I CCCC DDDDDDDDD SSSSSSSSS ANDN D,S/# AND !S into D Result=0 Parity
ZCMS 0011001 ZC I CCCC DDDDDDDDD SSSSSSSSS AND D,S/# AND S into D Result=0 Parity
ZCMS 0011010 ZC I CCCC DDDDDDDDD SSSSSSSSS OR D,S/# OR S into D Result=0 Parity
ZCMS 0011011 ZC I CCCC DDDDDDDDD SSSSSSSSS XOR D,S/# XOR S into D Result=0 Parity
ZCMS 0011100 ZC I CCCC DDDDDDDDD SSSSSSSSS MUXC D,S/# Copy C to bits in D using S as mask Result=0 Parity
ZCMS 0011101 ZC I CCCC DDDDDDDDD SSSSSSSSS MUXNC D,S/# Copy !C to bits in D using S as mask Result=0 Parity
ZCMS 0011110 ZC I CCCC DDDDDDDDD SSSSSSSSS MUXZ D,S/# Copy Z to bits in D using S as mask Result=0 Parity
ZCMS 0011111 ZC I CCCC DDDDDDDDD SSSSSSSSS MUXNZ D,S/# Copy !Z to bits in D using S as mask Result=0 Parity
ZCMS 0100000 ZC I CCCC DDDDDDDDD SSSSSSSSS ADD D,S/# Add S into D Result=0 unsigned Carry
ZCMS 0100001 ZC I CCCC DDDDDDDDD SSSSSSSSS SUB D,S/# Subtract S from D Result=0 unsigned Borrow
ZCMS 0100010 ZC I CCCC DDDDDDDDD SSSSSSSSS ADDX D,S/# Add extended S+C into D Z & (result=0) unsigned Carry
ZCMS 0100011 ZC I CCCC DDDDDDDDD SSSSSSSSS SUBX D,S/# Subtract extended S+C from D Z & (result=0) unsigned Borrow
ZCMS 0100100 ZC I CCCC DDDDDDDDD SSSSSSSSS SUMC D,S/# Sum either -S if C or S if !C into D Result=0 signed Overflow
ZCMS 0100101 ZC I CCCC DDDDDDDDD SSSSSSSSS SUMNC D,S/# Sum either S if C or -S if !C into D Result=0 signed Overflow
ZCMS 0100110 ZC I CCCC DDDDDDDDD SSSSSSSSS SUMZ D,S/# Sum either -S if Z or S if !Z into D Result=0 signed Overflow
ZCMS 0100111 ZC I CCCC DDDDDDDDD SSSSSSSSS SUMNZ D,S/# Sum either S if Z or -S if !Z into D Result=0 signed Overflow
ZCWS 0101000 ZC I CCCC DDDDDDDDD SSSSSSSSS MOV D,S/# Move S into D Result=0 S[31]
ZCWS 0101001 ZC I CCCC DDDDDDDDD SSSSSSSSS NOT D,S/# Set D to !S Result=0 S[31]
ZCWS 0101010 ZC I CCCC DDDDDDDDD SSSSSSSSS ABS D,S/# Set D to absolute S Result=0 S[31]
ZCWS 0101011 ZC I CCCC DDDDDDDDD SSSSSSSSS NEG D,S/# Set D to -S Result=0 S[31]
ZCWS 0101100 ZC I CCCC DDDDDDDDD SSSSSSSSS NEGC D,S/# Set D to either -S if C or S if !C Result=0 S[31]
ZCWS 0101101 ZC I CCCC DDDDDDDDD SSSSSSSSS NEGNC D,S/# Set D to either S if C or -S if !C Result=0 S[31]
ZCWS 0101110 ZC I CCCC DDDDDDDDD SSSSSSSSS NEGZ D,S/# Set D to either -S if Z or S if !Z Result=0 S[31]
ZCWS 0101111 ZC I CCCC DDDDDDDDD SSSSSSSSS NEGNZ D,S/# Set D to either -S if Z or S if !Z Result=0 S[31]
ZCMS 0110000 ZC I CCCC DDDDDDDDD SSSSSSSSS SETS D,S/# Move S[8..0] into D[8..0] Result=0 n/a
ZCMS 0110001 ZC I CCCC DDDDDDDDD SSSSSSSSS SETD D,S/# Move S[8..0] into D[17..9] Result=0 n/a
ZCMS 0110010 ZC I CCCC DDDDDDDDD SSSSSSSSS SETCOND D,S/# Move S[8..0] into D[21..18] Result=0 n/a
ZCMS 0110011 ZC I CCCC DDDDDDDDD SSSSSSSSS SETINST D,S/# Move S[8..0] into D[31..23] Result=0 n/a
ZCMS 0110100 ZC I CCCC DDDDDDDDD SSSSSSSSS MIN D,S/# Set D to S if unsigned (D<S) D=S unsigned(D<S)
ZCMS 0110101 ZC I CCCC DDDDDDDDD SSSSSSSSS MAX D,S/# Set D to S if unsigned (D=>S) D=S unsigned(D<S)
ZCMS 0110110 ZC I CCCC DDDDDDDDD SSSSSSSSS MINS D,S/# Set D to S if signed (D<S) D=S signed(D<S)
ZCMS 0110111 ZC I CCCC DDDDDDDDD SSSSSSSSS MAXS D,S/# Set D to S if signed (D=>S) D=S signed(D<S)
ZCMS 0111000 ZC I CCCC DDDDDDDDD SSSSSSSSS MUL D,S/#
ZCMS 0111001 ZC I CCCC DDDDDDDDD SSSSSSSSS MULS D,S/#
ZCWS 0111011 ZC I CCCC DDDDDDDDD SSSSSSSSS TOPBIT D,S/#
ZCWS 0111100 ZC I CCCC DDDDDDDDD SSSSSSSSS DECOD5 D,S/#
ZCWS 0111101 ZC I CCCC DDDDDDDDD SSSSSSSSS ESWAP8 D,S/#
ZCWS 0111110 ZC I CCCC DDDDDDDDD SSSSSSSSS SPLITW D,S/#
ZCWS 0111111 ZC I CCCC DDDDDDDDD SSSSSSSSS MERGEW D,S/#
ZCMS 1001000 ZC I CCCC DDDDDDDDD SSSSSSSSS INCMOD D,S/# Inc D modulo [#]S: D++; If D>S, D=0 Result=0 wrap?
ZCMS 1001001 ZC I CCCC DDDDDDDDD SSSSSSSSS DECMOD D,S/# Dec D modulo [#]S: D--; If D<0, D=S Result=0 wrap?
ZCMS 1001011 ZC I CCCC DDDDDDDDD SSSSSSSSS SUBR D,S/# Subtract (reverse) D=S-D result=0 unsigned Borrow
ZCMS 1001110 ZC I CCCC DDDDDDDDD SSSSSSSSS ROLNIB D,S/#
ZCMS 1001111 ZC I CCCC DDDDDDDDD SSSSSSSSS ROLBYTE D,S/#
--WS 1010xnn n0 I CCCC DDDDDDDDD SSSSSSSSS GETNIB D,S/#,#0..7
--MS 1010xnn n1 I CCCC DDDDDDDDD SSSSSSSSS SETNIB D,S/#,#0..7
--WS 1011xxn n0 I CCCC DDDDDDDDD SSSSSSSSS GETBYTE D,S/#,#0..3
--MS 1011xxn n1 I CCCC DDDDDDDDD SSSSSSSSS SETBYTE D,S/#,#0..3
ZCRS 1000000 ZC I CCCC DDDDDDDDD SSSSSSSSS TESTB D,S/#
ZCRS 1000001 ZC I CCCC DDDDDDDDD SSSSSSSSS TESTN D,S/# AND !S into D Result=0 Parity
ZCRS 1000010 ZC I CCCC DDDDDDDDD SSSSSSSSS TEST D,S/# AND S into D Result=0 Parity
ZCRS 1000011 ZC I CCCC DDDDDDDDD SSSSSSSSS CMP D,S/# Subtract S from D Result=0 unsigned Borrow
ZCRS 1000100 ZC I CCCC DDDDDDDDD SSSSSSSSS CMPX D,S/# Subtract extended S+C from D Z & (result=0) unsigned Borrow
ZCRS 1000101 ZC I CCCC DDDDDDDDD SSSSSSSSS CMPS D,S/# Compare signed D to S (ZC: D= Result=0 signed Borrow
ZCRS 1000110 ZC I CCCC DDDDDDDDD SSSSSSSSS CMPSX D,S/# Compare sign extended D to S+C Z & (result=0) signed Borrow
ZCRS 1000111 ZC I CCCC DDDDDDDDD SSSSSSSSS CMPR D,S/# Subtract (reverse) D=S-D result=0 unsigned Borrow
ZCMS 1001010 ZC I CCCC DDDDDDDDD SSSSSSSSS CMPSUB D,S/# Subtract S from D if D=>S: If D=>S, D -= S D=S unsigned(D=>S)
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------
ZCMS 0001000 ZC I CCCC DDDDDDDDD SSSSSSSSS ISOB D,S/# Isolate bit D[S/#]
ZCMS 0001001 ZC I CCCC DDDDDDDDD SSSSSSSSS NOTB D,S/# Invert bit D[S/#]
ZCMS 0001010 ZC I CCCC DDDDDDDDD SSSSSSSSS CLRB D,S/# Clear bit D[S/#] = 0
ZCMS 0001011 ZC I CCCC DDDDDDDDD SSSSSSSSS SETB D,S/# Set bit D[S/#] = 1
ZCMS 0001100 ZC I CCCC DDDDDDDDD SSSSSSSSS SETBC D,S/# Set bit D[S/#] = C
ZCMS 0001101 ZC I CCCC DDDDDDDDD SSSSSSSSS SETBNC D,S/# Set bit D[S/#] = !C
ZCMS 0001110 ZC I CCCC DDDDDDDDD SSSSSSSSS SETBZ D,S/# Set bit D[S/#] = Z
ZCMS 0001111 ZC I CCCC DDDDDDDDD SSSSSSSSS SETBNZ D,S/# Set bit D[S/#] = !Z
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------
[I]Now likely to be renamed PINOFF, PINNOT, PINCLR or PINLO, PINSET or PINHI, PINC, PINNC, PINZ, PINNZ[/I]
--L- 1111xxx 00 L CCCC DDDDDDDDD xxx000000 OFFP D/# Pin[D/#]=0; Dir=0
--L- 1111xxx 00 L CCCC DDDDDDDDD xxx000001 NOTP D/# Pin[D/#]=!Pin[D/#]; Dir=1
--L- 1111xxx 00 L CCCC DDDDDDDDD xxx000010 CLRP D/# Pin[D/#]= 0; Dir=1
--L- 1111xxx 00 L CCCC DDDDDDDDD xxx000011 SETP D/# Pin[D/#]= 1; Dir=1
--L- 1111xxx 00 L CCCC DDDDDDDDD xxx000100 SETPC D/# Pin[D/#]= C; Dir=1
--L- 1111xxx 00 L CCCC DDDDDDDDD xxx000101 SETPNC D/# Pin[D/#]=!C; Dir=1
--L- 1111xxx 00 L CCCC DDDDDDDDD xxx000110 SETPZ D/# Pin[D/#]= Z; Dir=1
--L- 1111xxx 00 L CCCC DDDDDDDDD xxx000111 SETPNZ D/# Pin[D/#]=!Z; Dir=1
ZCL- 1111xxx ZC L CCCC DDDDDDDDD xxx001000 GETP D/# !Z/C = Pin[D/#] via WZ/WC
ZCL- 1111xxx ZC L CCCC DDDDDDDDD xxx001001 GETNP D/# Z/!C = Pin[D/#] via WZ/WC
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------
--LS 1100110 0L I CCCC DDDDDDDDD SSSSSSSSS JP D/#,S/@ Jump to S/@ if PIN[D/#]
[s]--LS 1100110 1L I CCCC DDDDDDDDD SSSSSSSSS JPD D/#,S/@ Jump to S/@ if PIN[D/#] Delayed [/s]
--LS 1100111 0L I CCCC DDDDDDDDD SSSSSSSSS JNP D/#,S/@ Jump to S/@ if !PIN[D/#]
[s]--LS 1100111 1L I CCCC DDDDDDDDD SSSSSSSSS JNPD D/#,S/@ Jump to S/@ if !PIN[D/#] Delayed [/s]
ZCMS 1001000 ZC I CCCC DDDDDDDDD SSSSSSSSS DJZ D,S/@ Decrement D and Jump S/@ if Z
ZCMS 1001001 ZC I CCCC DDDDDDDDD SSSSSSSSS DJNZ D,S/@ Decrement D and Jump S/@ if NZ
ZCRS 1001010 ZC I CCCC DDDDDDDDD SSSSSSSSS TJZ D,S/@ Test D and Jump S/@ if Z
ZCRS 1001011 ZC I CCCC DDDDDDDDD SSSSSSSSS TJNZ D,S/@ Test D and Jump S/@ if NZ
--L- 1111xxx 00 L CCCC DDDDDDDDD xxx010100 JMPT0 D/# Jump Task 0
--L- 1111xxx 00 L CCCC DDDDDDDDD xxx010101 JMPT1 D/# Jump Task 1
--L- 1111xxx 00 L CCCC DDDDDDDDD xxx010110 JMPT2 D/# Jump Task 2
--L- 1111xxx 00 L CCCC DDDDDDDDD xxx010111 JMPT3 D/# Jump Task 3
ZCMS 0111010 ZC I CCCC DDDDDDDDD SSSSSSSSS JMPSW D,S/@ Z/C/PC --> D; S/# --> Z/C/PC
--R- 1111xxx ZC 0 CCCC DDDDDDDDD xxx110010 JMP D D[18:0] --> Z/C/PC via WZ/WC
---- 11101xx 00 0 CCCC 0 nnnnnnnnnnnnnnnnn JMP #abs D[18:0] --> Z/C/PC via WZ/WC
---- 11101xx 00 0 CCCC 1 nnnnnnnnnnnnnnnnn JMP @rel D[18:0] --> Z/C/PC via WZ/WC
--R- 1111xxx ZC 0 CCCC DDDDDDDDD xxx110011 CALL D Call using 4-level stack
---- 11101xx 00 1 CCCC 0 nnnnnnnnnnnnnnnnn CALL #abs Call using 4-level stack
---- 11101xx 00 1 CCCC 1 nnnnnnnnnnnnnnnnn CALL @rel Call using 4-level stack
ZC-- 1111xxx ZC 0 CCCC xxxxxxxxx xxx11100x RET Return using 4-level stack
--L- 1111xxx 00 L CCCC DDDDDDDDD xxx011010 PUSH D/# Push using 4-level stack
Z-W- 1111xxx Z0 0 CCCC DDDDDDDDD xxx100010 POP D Pop using 4-level stack
--R- 1111xxx ZC 0 CCCC DDDDDDDDD xxx110100 CALLA D Call using PTRA stack
---- 11101xx 01 0 CCCC 0 nnnnnnnnnnnnnnnnn CALLA #abs Call using PTRA stack
---- 11101xx 01 0 CCCC 1 nnnnnnnnnnnnnnnnn CALLA @rel Call using PTRA stack
ZC-- 1111xxx ZC 0 CCCC xxxxxxxxx xxx111010 RETA Return using PTRA stack
PUSHA D/# Push using PTRA stack
POPA Pop using PTRA stack
--R- 1111xxx ZC 0 CCCC DDDDDDDDD xxx110101 CALLB D Call using PTRB stack
---- 11101xx 01 1 CCCC 0 nnnnnnnnnnnnnnnnn CALLB #abs Call using PTRB stack
---- 11101xx 01 1 CCCC 1 nnnnnnnnnnnnnnnnn CALLB @rel Call using PTRB stack
ZC-- 1111xxx ZC 0 CCCC xxxxxxxxx xxx111011 RETB Return using PTRB stack
PUSHB D/# Push using PTRB stack
POPB Pop using PTRB stack
--R- wr 1111xxx ZC 0 CCCC DDDDDDDDD xxx110110 LINK D Call {0000000000000,Z,C,PC[16:0]} --> $1EF
---- wr 11101xx 10 0 CCCC 0 nnnnnnnnnnnnnnnnn LINK #abs Call {0000000000000,Z,C,PC[16:0]} --> $1EF
---- wr 11101xx 10 0 CCCC 1 nnnnnnnnnnnnnnnnn LINK @rel Call {0000000000000,Z,C,PC[16:0]} --> $1EF
---- wr 11101xx 10 1 CCCC 0 nnnnnnnnnnnnnnnnn LOCINST #abs 17-bit instruction address --> $1EF
---- wr 11101xx 10 1 CCCC 1 nnnnnnnnnnnnnnnnn LOCINST @rel 17-bit instruction address --> $1EF
--R- 1111xxx 00 0 CCCC DDDDDDDDD xxx110000 LOCPTRA D {D[16:0],00} --> PTRA
---- 11101xx 11 0 CCCC 0 nnnnnnnnnnnnnnnnn LOCPTRA #abs 17-bit instruction address << 2 --> PTRA
---- 11101xx 11 0 CCCC 1 nnnnnnnnnnnnnnnnn LOCPTRA @rel 17-bit instruction address << 2 --> PTRA
--R- 1111xxx 00 0 CCCC DDDDDDDDD xxx110001 LOCPTRB D {D[16:0],00} --> PTRB
---- 11101xx 11 1 CCCC 0 nnnnnnnnnnnnnnnnn LOCPTRB #abs 17-bit instruction address << 2 --> PTRB
---- 11101xx 11 1 CCCC 1 nnnnnnnnnnnnnnnnn LOCPTRB @rel 17-bit instruction address << 2 --> PTRB
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------
--L- 1111xxx 00 L CCCC DDDDDDDDD xxx011000 WAIT D/# Wait D/# clocks (0 same as 1)
ZCMS 1001100 ZC I CCCC DDDDDDDDD SSSSSSSSS WAITCNT D,S/# Wait CNT[31:0]=D; then D += S If WC, wait CNT[63:32]=D n/a WC=wait upper
--LS 1100010 0L I CCCC DDDDDDDDD SSSSSSSSS WAITPAE D/#,S/# Wait PortA Pins EQ: D==(PINS & S), If WC, wait timeout n/a C=timeout
--LS 1100010 1L I CCCC DDDDDDDDD SSSSSSSSS WAITPAN D/#,S/# Wait PortA Pins NE: D<>(PINS & S), If WC, wait timeout n/a C=timeout
--LS 1100011 0L I CCCC DDDDDDDDD SSSSSSSSS WAITPBE D/#,S/# Wait PortB Pins EQ: D==(PINS & S), If WC, wait timeout n/a C=timeout
--LS 1100011 1L I CCCC DDDDDDDDD SSSSSSSSS WAITPBN D/#,S/# Wait PortB Pins NE: D<>(PINS & S), If WC, wait timeout n/a C=timeout
--L- 1111xxx 00 L CCCC DDDDDDDDD xxx001010 WAITPR D/# Wait for Pin[D/#] Pos Edge
--L- 1111xxx 00 L CCCC DDDDDDDDD xxx001011 WAITPF D/# Wait for Pin[D/#] Neg Edge
--L- 1111xxx 00 L CCCC DDDDDDDDD xxx001100 WAITPX D/# Wait for Pin[D/#] Any Edge
--LS 1101001 0L I CCCC DDDDDDDDD SSSSSSSSS WAITVID D/#,S/# Wait for video generator to take D & S pixels n/a n/a
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------
--L- 1111xxx 00 L CCCC DDDDDDDDD xxx001110 SETPTRA D/# PTRA=D/#
--L- 1111xxx 00 L CCCC DDDDDDDDD xxx001111 SETPTRB D/# PTRB=D/#
Z-W- 1111xxx Z0 0 CCCC DDDDDDDDD xxx100000 GETPTRA D D=PTRA Result=0 n/a
Z-W- 1111xxx Z0 0 CCCC DDDDDDDDD xxx100001 GETPTRB D D=PTRB Result=0 n/a
--L- 1111xxx 00 L CCCC DDDDDDDDD xxx010000 SETINDA D/# Set INDA; INDA++ on each use
--L- 1111xxx 00 L CCCC DDDDDDDDD xxx010001 SETINDB D/# Set INDB; INDB++ on each use
--LS 1101000 0L I CCCC DDDDDDDDD SSSSSSSSS SETINDS D/#,S/# Set INDA=?/#; INDB=?/#
--L- 1111xxx 00 L CCCC DDDDDDDDD xxx010010 ADJINDA D/# Adj INDA+D/#
--L- 1111xxx 00 L CCCC DDDDDDDDD xxx010011 ADJINDB D/# Adj INDB+D/#
--LS 1101000 1L I CCCC DDDDDDDDD SSSSSSSSS ADJINDS D/#,S/# Adj INDA+?/#; INDB+?/#; INDA++ INDB++ each use
--L- 1111xxx 00 L CCCC DDDDDDDDD xxx001101 SETTASK D/#
--L- 1111xxx 00 L CCCC DDDDDDDDD xxx011001 SETVID D/#
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------
--LS 1100100 0L I CCCC DDDDDDDDD SSSSSSSSS MSGDIRA D/#,S/# Send D/# message to DIRA[S/#]
--LS 1100100 1L I CCCC DDDDDDDDD SSSSSSSSS MSGDIRB D/#,S/# Send D/# message to DIRB[S/#]
--LS 1100101 0L I CCCC DDDDDDDDD SSSSSSSSS MSGOUTA D/#,S/# Send D/# message to OUTA[S/#]
--LS 1100101 1L I CCCC DDDDDDDDD SSSSSSSSS MSGOUTB D/#,S/# Send D/# message to OUTB[S/#]
ZCWS 1001100 ZC I CCCC DDDDDDDDD SSSSSSSSS MSGINA D,S/# Recv D message from INA[S/#] (waits 64 clocks) C=timeout
ZCWS 1001101 ZC I CCCC DDDDDDDDD SSSSSSSSS MSGINB D,S/# Recv D message from INB[S/#] (waits 64 clocks) C=timeout
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------
---- 0000000 00 0 0000 000000000 000000000 NOP
ZCWS 0000111 ZC 1 CCCC DDDDDDDDD SSSSSSSSS SYSOP D,# (waits for hub, # determines four write-long enables)
--LS 1101001 1L I CCCC DDDDDDDDD SSSSSSSSS REP D/#,S/# Repeat D/#+1 loops of S/# instructions n/a n/a
---- 11100xx x0 n nnnn nnnnnnnnn nnnnnnnnn AUGS #23bits (appends n to upper bits of next immediate S in same task)
---- 11100xx x1 n nnnn nnnnnnnnn nnnnnnnnn AUGD #23bits (appends n to upper bits of next immediate D in same task)
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------
Comments
addr read write name background -------------------------------------------------------------------------- 000..1EE RAM RAM - - 1EF RAM RAM (used by LINK to save return address) 1F0 CNT - CNT DCACHE0 1F1 RND - RND DCACHE1 1F2 INA - INA DCACHE2 1F3 INB - INB DCACHE3 1F4 RAM RAM+OUTA OUTA - 1F5 RAM RAM+OUTB OUTB - 1F6 RAM RAM+DIRA DIRA - 1F7 RAM RAM+DIRB DIRB - 1F8 RAM RAM+CTRA CTRA - 1F9 RAM RAM+CTRB CTRB - 1FA RAM RAM+FRQA FRQA - 1FB RAM RAM+FRQB FRQB - 1FC PHSA PHSA PHSA ICACHE0 1FD PHSB PHSB PHSB ICACHE1 1FE indirect indirect INDA ICACHE2 1FF indirect indirect INDB ICACHE3Thanks for the info ozpropdev.Replies were as follows:
Yes, I think there are quite a few simple changes that could be made to simplify things.
Yes, one mnemonic. Yes MOVPIN or WRPIN/RDPIN might be better, and #NOT or #NOTPIN.
While I am at it, I think SETS / SETD / SETCOND / SETINST were nicer as MOVS / MOVD / MOVCOND / MOVI or MOVINST.
Thoughts?
OFFP/NOTP/CLRP/SETP/SETPC/SETPNC/SETPZ/SETPNZ
replaced with the single instruction...
WRPIN D/#, #0 / #1 / #NOT / #OFF / #Z / #C / #NZ / NC
and...
GETP/GETNP
replaced with...
RDPIN [#NOT], D/# WZ,WC
thoughts??
Does this make sense...
ISOB/NOTB/CLRB/SETB/SETBC/SETBNC/SETBZ/SETBNZ
replaced with the single instruction...
WRBITS #0/#LO/#1/#HI/#NOT/#ISO/#Z/#C/#NZ/#NC, D,S/#
(maybe change the operand positions???)
#ISO might be (not quite sure what it does)
RDBITS #ISO, D, S/#
Similarly...
SETPTRA, SETPTRB, SETINDA, SETINDB, SETINDS, GETPTRA, GETPTRB, ADJINDA, ADJINDB, ADJINDS
might be better as...
SET #PTRA/#PTRB/#INDA/#INDB/#INDS, D/# [,S/#]
GET #PTRA/#PTRB, D
ADJ #INDA/#INDB/#INDS, D/# [,S/#]
One general SETPIN with odd modes is non-optimal, particularly given the reserved names. Much prefer the simpler case for readability, ease of discovery, etc...
I also prefer the simple D & S argument form. That's an awful nice attribute of PASM. Going to 2 and sometimes 3 and maybe one is something I would prefer minimized.
Focusing on the number of primary instruction mnemonics at the expense of more arguments and or fiddly keyword space doesn't add value, IMHO.
I would like to see any suggestions for simple name changes wait until the work is mostly done. At this point, it is really best that Chip use names that make the most sense to him.
So, I am happy that this is about semantics and not about names!:)
Heater has correctly identified the area of stack memory and utilization to be one of those areas that troubles new(and old) users and could use a good semantic overhaul. When I first encounter the area, I was surprised that "stack" was not a reserved word with special meaning to the compiler. The user shouldn't be forced to use this keyword, but it should be a keyword with special meaning.
Do you need these pin instructions? I know they are convenient, but if they didn't exist, would you really suffer? I realize that this is not an issue of semantics, but this is your thread so I know you won't miss my question… and I don't want to start a new thread just to ask you a question. Would it slow down execution?
Rich
------------------------------------------------------------------------------------------- ZCWS 0000000 ZC 1 CCCC DDDDDDDDD SSSSSSSSS RDBYTE D,PTRA/PTRB (waits for hub) ZCWS 0000001 ZC 1 CCCC DDDDDDDDD SSSSSSSSS RDBYTEC D,PTRA/PTRB (waits for hub if dcache miss) ZCWS 0000010 ZC 1 CCCC DDDDDDDDD SSSSSSSSS RDWORD D,PTRA/PTRB (waits for hub) ZCWS 0000011 ZC 1 CCCC DDDDDDDDD SSSSSSSSS RDWORDC D,PTRA/PTRB (waits for hub if dcache miss) ZCWS 0000100 ZC 1 CCCC DDDDDDDDD SSSSSSSSS RDLONG D,PTRA/PTRB (waits for hub) ZCWS 0000101 ZC 1 CCCC DDDDDDDDD SSSSSSSSS RDLONGC D,PTRA/PTRB (waits for hub if dcache miss) ZCWS 0000110 ZC 1 CCCC DDDDDDDDD SSSSSSSSS RDQUAD D,PTRA/PTRB (waits for hub) --LS 1100000 0L 1 CCCC DDDDDDDDD SSSSSSSSS WRBYTE D/#,PTRA/PTRB (waits for hub) --LS 1100000 1L 1 CCCC DDDDDDDDD SSSSSSSSS WRWORD D/#,PTRA/PTRB (waits for hub) --LS 1100001 0L 1 CCCC DDDDDDDDD SSSSSSSSS WRLONG D/#,PTRA/PTRB (waits for hub) --LS 1100001 1L 1 CCCC DDDDDDDDD SSSSSSSSS WRQUAD D/#,PTRA/PTRB (waits for hub, zero-extends #) ---- 1111xxx 00 0 CCCC xxxxxxxxx xxx111100 DCACHEX (invalidate data cache) ---- 1111xxx 00 0 CCCC xxxxxxxxx xxx111101 ICACHEX (invalidate instruction cache) ------------------------------------------------------------------------------------------- ZCMS 0010000 ZC I CCCC DDDDDDDDD SSSSSSSSS ROR D,S/# ZCMS 0010001 ZC I CCCC DDDDDDDDD SSSSSSSSS ROL D,S/# ZCMS 0010010 ZC I CCCC DDDDDDDDD SSSSSSSSS SHR D,S/# ZCMS 0010011 ZC I CCCC DDDDDDDDD SSSSSSSSS SHL D,S/# ZCMS 0010100 ZC I CCCC DDDDDDDDD SSSSSSSSS RCR D,S/# ZCMS 0010101 ZC I CCCC DDDDDDDDD SSSSSSSSS RCL D,S/# ZCMS 0010110 ZC I CCCC DDDDDDDDD SSSSSSSSS SAR D,S/# ZCMS 0010111 ZC I CCCC DDDDDDDDD SSSSSSSSS REV D,S/# ZCMS 0011000 ZC I CCCC DDDDDDDDD SSSSSSSSS ANDN D,S/# ZCMS 0011001 ZC I CCCC DDDDDDDDD SSSSSSSSS AND D,S/# ZCMS 0011010 ZC I CCCC DDDDDDDDD SSSSSSSSS OR D,S/# ZCMS 0011011 ZC I CCCC DDDDDDDDD SSSSSSSSS XOR D,S/# ZCMS 0011100 ZC I CCCC DDDDDDDDD SSSSSSSSS MUXC D,S/# ZCMS 0011101 ZC I CCCC DDDDDDDDD SSSSSSSSS MUXNC D,S/# ZCMS 0011110 ZC I CCCC DDDDDDDDD SSSSSSSSS MUXZ D,S/# ZCMS 0011111 ZC I CCCC DDDDDDDDD SSSSSSSSS MUXNZ D,S/# ZCMS 0100000 ZC I CCCC DDDDDDDDD SSSSSSSSS ADD D,S/# ZCMS 0100001 ZC I CCCC DDDDDDDDD SSSSSSSSS SUB D,S/# ZCMS 0100010 ZC I CCCC DDDDDDDDD SSSSSSSSS ADDX D,S/# ZCMS 0100011 ZC I CCCC DDDDDDDDD SSSSSSSSS SUBX D,S/# ZCMS 0100100 ZC I CCCC DDDDDDDDD SSSSSSSSS SUMC D,S/# ZCMS 0100101 ZC I CCCC DDDDDDDDD SSSSSSSSS SUMNC D,S/# ZCMS 0100110 ZC I CCCC DDDDDDDDD SSSSSSSSS SUMZ D,S/# ZCMS 0100111 ZC I CCCC DDDDDDDDD SSSSSSSSS SUMNZ D,S/# ZCWS 0101000 ZC I CCCC DDDDDDDDD SSSSSSSSS MOV D,S/# ZCWS 0101001 ZC I CCCC DDDDDDDDD SSSSSSSSS NOT D,S/# ZCWS 0101010 ZC I CCCC DDDDDDDDD SSSSSSSSS ABS D,S/# ZCWS 0101011 ZC I CCCC DDDDDDDDD SSSSSSSSS NEG D,S/# ZCWS 0101100 ZC I CCCC DDDDDDDDD SSSSSSSSS NEGC D,S/# ZCWS 0101101 ZC I CCCC DDDDDDDDD SSSSSSSSS NEGNC D,S/# ZCWS 0101110 ZC I CCCC DDDDDDDDD SSSSSSSSS NEGZ D,S/# ZCWS 0101111 ZC I CCCC DDDDDDDDD SSSSSSSSS NEGNZ D,S/# ZCMS 0110000 ZC I CCCC DDDDDDDDD SSSSSSSSS SETS D,S/# ZCMS 0110001 ZC I CCCC DDDDDDDDD SSSSSSSSS SETD D,S/# ZCMS 0110010 ZC I CCCC DDDDDDDDD SSSSSSSSS SETCOND D,S/# ZCMS 0110011 ZC I CCCC DDDDDDDDD SSSSSSSSS SETINST D,S/# ZCMS 0110100 ZC I CCCC DDDDDDDDD SSSSSSSSS MIN D,S/# ZCMS 0110101 ZC I CCCC DDDDDDDDD SSSSSSSSS MAX D,S/# ZCMS 0110110 ZC I CCCC DDDDDDDDD SSSSSSSSS MINS D,S/# ZCMS 0110111 ZC I CCCC DDDDDDDDD SSSSSSSSS MAXS D,S/# ZCMS 0111000 ZC I CCCC DDDDDDDDD SSSSSSSSS MUL D,S/# ZCMS 0111001 ZC I CCCC DDDDDDDDD SSSSSSSSS MULS D,S/# ZCWS 0111011 ZC I CCCC DDDDDDDDD SSSSSSSSS TOPBIT D,S/# ZCWS 0111100 ZC I CCCC DDDDDDDDD SSSSSSSSS DECOD5 D,S/# ZCWS 0111101 ZC I CCCC DDDDDDDDD SSSSSSSSS ESWAP8 D,S/# ZCWS 0111110 ZC I CCCC DDDDDDDDD SSSSSSSSS SPLITW D,S/# ZCWS 0111111 ZC I CCCC DDDDDDDDD SSSSSSSSS MERGEW D,S/# ZCMS 1001000 ZC I CCCC DDDDDDDDD SSSSSSSSS INCMOD D,S/# ZCMS 1001001 ZC I CCCC DDDDDDDDD SSSSSSSSS DECMOD D,S/# ZCMS 1001011 ZC I CCCC DDDDDDDDD SSSSSSSSS SUBR D,S/# ZCMS 1001110 ZC I CCCC DDDDDDDDD SSSSSSSSS ROLNIB D,S/# ZCMS 1001111 ZC I CCCC DDDDDDDDD SSSSSSSSS ROLBYTE D,S/# --WS 1010xnn n0 I CCCC DDDDDDDDD SSSSSSSSS GETNIB D,S/#,#0..7 --MS 1010xnn n1 I CCCC DDDDDDDDD SSSSSSSSS SETNIB D,S/#,#0..7 --WS 1011xxn n0 I CCCC DDDDDDDDD SSSSSSSSS GETBYTE D,S/#,#0..3 --MS 1011xxn n1 I CCCC DDDDDDDDD SSSSSSSSS SETBYTE D,S/#,#0..3 ZCRS 1000000 ZC I CCCC DDDDDDDDD SSSSSSSSS TESTB D,S/# ZCRS 1000001 ZC I CCCC DDDDDDDDD SSSSSSSSS TESTN D,S/# ZCRS 1000010 ZC I CCCC DDDDDDDDD SSSSSSSSS TEST D,S/# ZCRS 1000011 ZC I CCCC DDDDDDDDD SSSSSSSSS CMP D,S/# ZCRS 1000100 ZC I CCCC DDDDDDDDD SSSSSSSSS CMPX D,S/# ZCRS 1000101 ZC I CCCC DDDDDDDDD SSSSSSSSS CMPS D,S/# ZCRS 1000110 ZC I CCCC DDDDDDDDD SSSSSSSSS CMPSX D,S/# ZCRS 1000111 ZC I CCCC DDDDDDDDD SSSSSSSSS CMPR D,S/# ZCMS 1001010 ZC I CCCC DDDDDDDDD SSSSSSSSS CMPSUB D,S/# ------------------------------------------------------------------------------------------- ZCMS 0001000 ZC I CCCC DDDDDDDDD SSSSSSSSS ISOB D,S/# ZCMS 0001001 ZC I CCCC DDDDDDDDD SSSSSSSSS NOTB D,S/# ZCMS 0001010 ZC I CCCC DDDDDDDDD SSSSSSSSS CLRB D,S/# ZCMS 0001011 ZC I CCCC DDDDDDDDD SSSSSSSSS SETB D,S/# ZCMS 0001100 ZC I CCCC DDDDDDDDD SSSSSSSSS SETBC D,S/# ZCMS 0001101 ZC I CCCC DDDDDDDDD SSSSSSSSS SETBNC D,S/# ZCMS 0001110 ZC I CCCC DDDDDDDDD SSSSSSSSS SETBZ D,S/# ZCMS 0001111 ZC I CCCC DDDDDDDDD SSSSSSSSS SETBNZ D,S/# ------------------------------------------------------------------------------------------- --L- 1111xxx 00 L CCCC DDDDDDDDD xxx000000 OFFP D/# (pin operations that affect DIR and OUT simultaneously) --L- 1111xxx 00 L CCCC DDDDDDDDD xxx000001 NOTP D/# --L- 1111xxx 00 L CCCC DDDDDDDDD xxx000010 CLRP D/# --L- 1111xxx 00 L CCCC DDDDDDDDD xxx000011 SETP D/# --L- 1111xxx 00 L CCCC DDDDDDDDD xxx000100 SETPC D/# --L- 1111xxx 00 L CCCC DDDDDDDDD xxx000101 SETPNC D/# --L- 1111xxx 00 L CCCC DDDDDDDDD xxx000110 SETPZ D/# --L- 1111xxx 00 L CCCC DDDDDDDDD xxx000111 SETPNZ D/# ZCL- 1111xxx ZC L CCCC DDDDDDDDD xxx001000 GETP D/# (pin into !Z/C via WZ/WC) ZCL- 1111xxx ZC L CCCC DDDDDDDDD xxx001001 GETNP D/# (pin into Z/!C via WZ/WC) ------------------------------------------------------------------------------------------- ZCMS 1001000 ZC I CCCC DDDDDDDDD SSSSSSSSS DJZ D,S/@ ZCMS 1001001 ZC I CCCC DDDDDDDDD SSSSSSSSS DJNZ D,S/@ ZCRS 1001010 ZC I CCCC DDDDDDDDD SSSSSSSSS TJZ D,S/@ ZCRS 1001011 ZC I CCCC DDDDDDDDD SSSSSSSSS TJNZ D,S/@ --L- 1111xxx 00 L CCCC DDDDDDDDD xxx010100 JMPT0 D/# --L- 1111xxx 00 L CCCC DDDDDDDDD xxx010101 JMPT1 D/# --L- 1111xxx 00 L CCCC DDDDDDDDD xxx010110 JMPT2 D/# --L- 1111xxx 00 L CCCC DDDDDDDDD xxx010111 JMPT3 D/# ZCMS 0111010 ZC I CCCC DDDDDDDDD SSSSSSSSS JMPSW D,S/@ (save Z/C/PC into D, load Z/C/PC from S/#) --R- 1111xxx ZC 0 CCCC DDDDDDDDD xxx110010 JMP D (D[18:17] into Z/C via WZ/WC for JMP..LINK D) ---- 11101xx 00 0 CCCC 0 nnnnnnnnnnnnnnnnn JMP #abs ---- 11101xx 00 0 CCCC 1 nnnnnnnnnnnnnnnnn JMP @rel --R- 1111xxx ZC 0 CCCC DDDDDDDDD xxx110011 CALL D (call using 4-level stack) ---- 11101xx 00 1 CCCC 0 nnnnnnnnnnnnnnnnn CALL #abs ---- 11101xx 00 1 CCCC 1 nnnnnnnnnnnnnnnnn CALL @rel ZC-- 1111xxx ZC 0 CCCC xxxxxxxxx xxx11100x RET (return using 4-level stack) --L- 1111xxx 00 L CCCC DDDDDDDDD xxx011010 PUSH D/# (pushes into 4-level stack) Z-W- 1111xxx Z0 0 CCCC DDDDDDDDD xxx100010 POP D (pops from 4-level stack) --R- 1111xxx ZC 0 CCCC DDDDDDDDD xxx110100 CALLA D (call using PTRA) ---- 11101xx 01 0 CCCC 0 nnnnnnnnnnnnnnnnn CALLA #abs ---- 11101xx 01 0 CCCC 1 nnnnnnnnnnnnnnnnn CALLA @rel ZC-- 1111xxx ZC 0 CCCC xxxxxxxxx xxx111010 RETA (return using PTRA) PUSHA D/# (alias for WRLONG D/#,PTRA++) POPA (alias for RDLONG D,--PTRA) --R- 1111xxx ZC 0 CCCC DDDDDDDDD xxx110101 CALLB D (call using PTRB) ---- 11101xx 01 1 CCCC 0 nnnnnnnnnnnnnnnnn CALLB #abs ---- 11101xx 01 1 CCCC 1 nnnnnnnnnnnnnnnnn CALLB @rel ZC-- 1111xxx ZC 0 CCCC xxxxxxxxx xxx111011 RETB (return using PTRB) PUSHB D/# (alias for WRLONG D/#,PTRB++) POPB (alias for RDLONG D,--PTRB) --R- wr 1111xxx ZC 0 CCCC DDDDDDDDD xxx110110 LINK D (jump and write {%0000000000000,Z,C,PC[16:0]} to $1EF) ---- wr 11101xx 10 0 CCCC 0 nnnnnnnnnnnnnnnnn LINK #abs (jump and write {%0000000000000,Z,C,PC[16:0]} to $1EF) ---- wr 11101xx 10 0 CCCC 1 nnnnnnnnnnnnnnnnn LINK @rel (jump and write {%0000000000000,Z,C,PC[16:0]} to $1EF) ---- wr 11101xx 10 1 CCCC 0 nnnnnnnnnnnnnnnnn LOCINST #abs (write 17-bit instruction address to $1EF) ---- wr 11101xx 10 1 CCCC 1 nnnnnnnnnnnnnnnnn LOCINST @rel (write 17-bit instruction address to $1EF) --R- 1111xxx 00 0 CCCC DDDDDDDDD xxx110000 LOCPTRA D (PTRA = {D[16:0],%00}) ---- 11101xx 11 0 CCCC 0 nnnnnnnnnnnnnnnnn LOCPTRA #abs (write 17-bit instruction address << 2 to PTRA) ---- 11101xx 11 0 CCCC 1 nnnnnnnnnnnnnnnnn LOCPTRA @rel (write 17-bit instruction address << 2 to PTRA) --R- 1111xxx 00 0 CCCC DDDDDDDDD xxx110001 LOCPTRB D (PTRB = {D[16:0],%00}) ---- 11101xx 11 1 CCCC 0 nnnnnnnnnnnnnnnnn LOCPTRB #abs (write 17-bit instruction address << 2 to PTRB) ---- 11101xx 11 1 CCCC 1 nnnnnnnnnnnnnnnnn LOCPTRB @rel (write 17-bit instruction address << 2 to PTRB) ------------------------------------------------------------------------------------------- --L- 1111xxx 00 L CCCC DDDDDDDDD xxx011000 WAIT D/# (waits 1+ clocks, 0 same as 1) ZCMS 1001100 ZC I CCCC DDDDDDDDD SSSSSSSSS WAITCNT D,S/# --LS 1100010 0L I CCCC DDDDDDDDD SSSSSSSSS WAITPAE D/#,S/# (waits for INA) --LS 1100010 1L I CCCC DDDDDDDDD SSSSSSSSS WAITPAN D/#,S/# (waits for INA) --LS 1100011 0L I CCCC DDDDDDDDD SSSSSSSSS WAITPBE D/#,S/# (waits for INB) --LS 1100011 1L I CCCC DDDDDDDDD SSSSSSSSS WAITPBN D/#,S/# (waits for INB) --L- 1111xxx 00 L CCCC DDDDDDDDD xxx001010 WAITPR D/# (waits for pos edge on pin) --L- 1111xxx 00 L CCCC DDDDDDDDD xxx001011 WAITPF D/# (waits for neg edge on pin) --L- 1111xxx 00 L CCCC DDDDDDDDD xxx001100 WAITPX D/# (waits for any edge on pin) --LS 1101001 0L I CCCC DDDDDDDDD SSSSSSSSS WAITVID D/#,S/# (waits for vid) ------------------------------------------------------------------------------------------- --L- 1111xxx 00 L CCCC DDDDDDDDD xxx001110 SETPTRA D/# --L- 1111xxx 00 L CCCC DDDDDDDDD xxx001111 SETPTRB D/# Z-W- 1111xxx Z0 0 CCCC DDDDDDDDD xxx100000 GETPTRA D Z-W- 1111xxx Z0 0 CCCC DDDDDDDDD xxx100001 GETPTRB D --L- 1111xxx 00 L CCCC DDDDDDDDD xxx010000 SETINDA D/# (set INDA/INDB, INDA/INDB increment on each use) --L- 1111xxx 00 L CCCC DDDDDDDDD xxx010001 SETINDB D/# --LS 1101000 0L I CCCC DDDDDDDDD SSSSSSSSS SETINDS D/#,S/# --L- 1111xxx 00 L CCCC DDDDDDDDD xxx010010 ADJINDA D/# (adjust INDA/INDB by adding value) --L- 1111xxx 00 L CCCC DDDDDDDDD xxx010011 ADJINDB D/# --LS 1101000 1L I CCCC DDDDDDDDD SSSSSSSSS ADJINDS D/#,S/# --L- 1111xxx 00 L CCCC DDDDDDDDD xxx001101 SETTASK D/# --L- 1111xxx 00 L CCCC DDDDDDDDD xxx011001 SETVID D/# -------------------------------------------------------------------------------------------- --LS 1100100 0L I CCCC DDDDDDDDD SSSSSSSSS MSGDIRA D/#,S/# --LS 1100100 1L I CCCC DDDDDDDDD SSSSSSSSS MSGDIRB D/#,S/# --LS 1100101 0L I CCCC DDDDDDDDD SSSSSSSSS MSGOUTA D/#,S/# --LS 1100101 1L I CCCC DDDDDDDDD SSSSSSSSS MSGOUTB D/#,S/# ZCWS 1001100 ZC I CCCC DDDDDDDDD SSSSSSSSS MSGINA D,S/# (waits up to 64 clocks to receive %010_data32 message on INA, C=timeout) ZCWS 1001101 ZC I CCCC DDDDDDDDD SSSSSSSSS MSGINB D,S/# (waits up to 64 clocks to receive %010_data32 message on INB, C=timeout) ------------------------------------------------------------------------------------------- ---- 0000000 00 0 0000 000000000 000000000 NOP ZCWS 0000111 ZC 1 CCCC DDDDDDDDD SSSSSSSSS SYSOP D,# (waits for hub, # determines four write-long enables) --LS 1101001 1L I CCCC DDDDDDDDD SSSSSSSSS REP D/#,S/# ---- 11100xx x0 n nnnn nnnnnnnnn nnnnnnnnn AUGS #23bits (appends n to upper bits of next immediate S in same task) ---- 11100xx x1 n nnnn nnnnnnnnn nnnnnnnnn AUGD #23bits (appends n to upper bits of next immediate D in same task) --------------------------------------------------------------------------------------------However, they do make life easier to write directly to a pin (each of the 64 pins can be addressed, but only 1 at a time), so it does make some drivers much simpler to code, and perhaps faster to execute.
You know, once we get the FPGA, it might be worthwhile to knock out some little samples and truth tables. I had some notes on the other design that were getting there.
So if the pin instructions were PINOFF, PINNOT, PINCLR/PINLO, PINSET/PINHI, PINC, PINNC, PINZ, PINNZ they could be under the heading PINxxx and be describe simply. They can then be counted as a single group of instructions - means a lot when you say you have 160+ instructions or 80 base instructions. We don't want it to look too complex (remember the comments about the 400+ instructions.
And yes, its worthwhile discussing while Chip is doing other things. We can suggest, but of course he is the arbiter. Currently we don't have an fpga to really play with so we might as well discuss something useful.
I would like comments to go with some of those more obscure instructions if anyone has the time and knows what they do. (We don't need to bother Chip).
Truth tables isn't quite right, but for the logical operators. For other ones, there are key inputs and outputs, like the ones we would use for testing that would be nice to have.
Remember how Moto did it's programmers manuals? Sometimes a code fragment made sense. Other times, the edge conditions and boundary conditions were listed along with unambigious arguments. That kind of thing.
The groups you have make sense. Rather than pack the header info into the instruction, which reduced clarity, simply add headers to the groups! Then the instructions can be as they mostly are, easy to remember.
PIN, PIN, PIN, PIN...
So we have group header
Pins
SETP, NOTP, CLRP, etc...
Less overall to type, groups remembered once, etc...
Of course a list of instructions looks complex! So does a simple number of instructions. In some basic sense, they are, but grouping things simply does a lot more damage on that problem than attempting to sort it all in the name of things, which generally fattens those up a lot, adds no more value than the group headings and other simple presentation devices do, and we type a lot more than we otherwise would in the end.
Most of the instructions names are down to the nubs. There are some like the wait ones that aren't but they sure read well.
So yeah, I really like the groups and would add headers and when we produce some reference material, can add some stuff there that I mentioned above. I don't mean to imply you should do it, or that it needs to be done now either. Wasn't my intent at all. I like your lists. And they are useful, and a great start for lots of other things!
If this chip is too similar to the original P2, no one (i.e. high volume customers) will use the what was originally supposed to be P2 when it is finally released, and, even worse, the original P2 might never be released because there won't be enough incentive to release it. I probably missed something because there's been too much going on for me to keep up with, but wasn't this new chip supposed to just be something new that was a lot faster and had more cogs, pins, ram, etc. to increase the Propeller's usability and popularity so Parallax could get enough money to make what was supposed to be the P2?
Does Parallax have names for these two chips yet? The original P2 is the P8X32C, right? What's the new 16 cog chip called? found it... P16X512x
electrodude
EDIT: And yes, there will be 500 instructions in this chip if things keep going the way they are now. Most of the instructions on the original P2 were added because they were necessary to complete recently added features or because they were easy. For example, taking away the R bit means you have to add TARG and friends, and adding hubexec means you have to add AUGx and screw up jmpret. Most of the instructions in the table above aren't on the P1 - they were taken directly from the P2. There are already 169 instructions, up from only 64 on the P1.
Is it really worth it to rewrite the P2? If you're going to add almost everything in the original P2, why not just strip down the P2 instead of building everything back up on top of the P1?
Reading a lot of comments this past week, I don't think the fancy video hardware is going to go in this 16-cog chip. It may have been a big part of what made it infeasible at 180 nm.
I too am just resigned to taking what I can get from the P2 project.
It's also a matter of perspective, is it fortifying and building up a P1? or is it stripping down a P2? Isn't it kind of the same thing at this point?
P2 is obviously going to morph into something unique, with its own reason to exist.
The awesome thing about the hardware description code at this point, is it can be moved around in large chunks. Entire features brought in or left out with a copy and paste and some glue statements. Size up or down some array elements. etc.
VGA only, at this process, makes a lot of sense too. TV, Component and some other things we might want can be done in software. And they can be done well too.
Some day, when we can get the other design in a process to match it, that video system is really great! And by the time it gets realized, the display tech will be well matched to it. Honestly, that video system is a great piece of engineering that needs to get out there someday.
But this one will punch well above it's weight, and it will work more P1 style, which is just fine. We know how to do that too.
What Chip is doing is a refactor, taking the good things he can, optimizing for power, and in a few cases, like the pins, thinking in new ways to realize some of the basic goals he has for the device.
I doubt we will see that huge number of instructions. And we really should maximize what we can do in this process! It's to the benefit of everyone IMHO. Let him work a bit. Good things are gonna happen.
Well, I see it a few ways. There is the programmers quick reference, and some programming model, block diagram, data sheet. For a lot of people, that's the primary tool.
Having a page per instruction is killer otherwise! That's where a code sample, key cases, truth tables, logic diagrams, etc.. go. Some of those pages won't have much, but others will have a ton.
Wrap that all into an online system, and anybody anywhere can type part of an instruction, get a code snippet, understand the cases they need to, and carry on just fine, quick and easy.
Or, if they are older school, they can print it off and have a manual too. Personally, I'm beyond manuals when I can get resources like that. And as time goes on, those pages can be augmented with whatever comes up on the support side of things too. No need to republish, or anything like that either. Simply change the date stamp, and or post up a notification, and everybody goes to it when they need to / want to.
What I still think is nice for manuals, books, is more cookbook, how to, philosophy, tutorial types of things. Moto had it right way back when, and that's precisely what they did. One page per, and some were filled, others simple, with wide margins so people could scribble all over the place. Map that to the tech we have today, and it's excellent, easy to maintain, and the work to populate it can be distributed among as many people as is necessary, up to one person per instruction!
Imagine we all took 5 - 10 instructions and over the course of a month, produced those pages, simple. We would be done! And it would be excellent!
Somebody else can package that down into the lean, mean reference docs, etc...
Thanks for the formatted list!
@Chip
Do the delayed JPD and JNPD need to be removed from the list?
------------------------------------------------------------------------------------------- ZCWS 0000000 ZC 1 CCCC DDDDDDDDD SSSSSSSSS RDBYTE D,PTRA/PTRB (waits for hub) ZCWS 0000001 ZC 1 CCCC DDDDDDDDD SSSSSSSSS RDBYTEC D,PTRA/PTRB (waits for hub if dcache miss) ZCWS 0000010 ZC 1 CCCC DDDDDDDDD SSSSSSSSS RDWORD D,PTRA/PTRB (waits for hub) ZCWS 0000011 ZC 1 CCCC DDDDDDDDD SSSSSSSSS RDWORDC D,PTRA/PTRB (waits for hub if dcache miss) ZCWS 0000100 ZC 1 CCCC DDDDDDDDD SSSSSSSSS RDLONG D,PTRA/PTRB (waits for hub) ZCWS 0000101 ZC 1 CCCC DDDDDDDDD SSSSSSSSS RDLONGC D,PTRA/PTRB (waits for hub if dcache miss) ZCWS 0000110 ZC 1 CCCC DDDDDDDDD SSSSSSSSS RDQUAD D,PTRA/PTRB (waits for hub) --LS 1100000 0L 1 CCCC DDDDDDDDD SSSSSSSSS WRBYTE D/#,PTRA/PTRB (waits for hub) --LS 1100000 1L 1 CCCC DDDDDDDDD SSSSSSSSS WRWORD D/#,PTRA/PTRB (waits for hub) --LS 1100001 0L 1 CCCC DDDDDDDDD SSSSSSSSS WRLONG D/#,PTRA/PTRB (waits for hub) --LS 1100001 1L 1 CCCC DDDDDDDDD SSSSSSSSS WRQUAD D/#,PTRA/PTRB (waits for hub, zero-extends #) ---- 1111xxx 00 0 CCCC xxxxxxxxx xxx111100 DCACHEX (invalidate data cache) ---- 1111xxx 00 0 CCCC xxxxxxxxx xxx111101 ICACHEX (invalidate instruction cache) ------------------------------------------------------------------------------------------- ZCMS 0010000 ZC I CCCC DDDDDDDDD SSSSSSSSS ROR D,S/# ZCMS 0010001 ZC I CCCC DDDDDDDDD SSSSSSSSS ROL D,S/# ZCMS 0010010 ZC I CCCC DDDDDDDDD SSSSSSSSS SHR D,S/# ZCMS 0010011 ZC I CCCC DDDDDDDDD SSSSSSSSS SHL D,S/# ZCMS 0010100 ZC I CCCC DDDDDDDDD SSSSSSSSS RCR D,S/# ZCMS 0010101 ZC I CCCC DDDDDDDDD SSSSSSSSS RCL D,S/# ZCMS 0010110 ZC I CCCC DDDDDDDDD SSSSSSSSS SAR D,S/# ZCMS 0010111 ZC I CCCC DDDDDDDDD SSSSSSSSS REV D,S/# ZCMS 0011000 ZC I CCCC DDDDDDDDD SSSSSSSSS ANDN D,S/# ZCMS 0011001 ZC I CCCC DDDDDDDDD SSSSSSSSS AND D,S/# ZCMS 0011010 ZC I CCCC DDDDDDDDD SSSSSSSSS OR D,S/# ZCMS 0011011 ZC I CCCC DDDDDDDDD SSSSSSSSS XOR D,S/# ZCMS 0011100 ZC I CCCC DDDDDDDDD SSSSSSSSS MUXC D,S/# ZCMS 0011101 ZC I CCCC DDDDDDDDD SSSSSSSSS MUXNC D,S/# ZCMS 0011110 ZC I CCCC DDDDDDDDD SSSSSSSSS MUXZ D,S/# ZCMS 0011111 ZC I CCCC DDDDDDDDD SSSSSSSSS MUXNZ D,S/# ZCMS 0100000 ZC I CCCC DDDDDDDDD SSSSSSSSS ADD D,S/# ZCMS 0100001 ZC I CCCC DDDDDDDDD SSSSSSSSS SUB D,S/# ZCMS 0100010 ZC I CCCC DDDDDDDDD SSSSSSSSS ADDX D,S/# ZCMS 0100011 ZC I CCCC DDDDDDDDD SSSSSSSSS SUBX D,S/# ZCMS 0100100 ZC I CCCC DDDDDDDDD SSSSSSSSS SUMC D,S/# ZCMS 0100101 ZC I CCCC DDDDDDDDD SSSSSSSSS SUMNC D,S/# ZCMS 0100110 ZC I CCCC DDDDDDDDD SSSSSSSSS SUMZ D,S/# ZCMS 0100111 ZC I CCCC DDDDDDDDD SSSSSSSSS SUMNZ D,S/# ZCWS 0101000 ZC I CCCC DDDDDDDDD SSSSSSSSS MOV D,S/# ZCWS 0101001 ZC I CCCC DDDDDDDDD SSSSSSSSS NOT D,S/# ZCWS 0101010 ZC I CCCC DDDDDDDDD SSSSSSSSS ABS D,S/# ZCWS 0101011 ZC I CCCC DDDDDDDDD SSSSSSSSS NEG D,S/# ZCWS 0101100 ZC I CCCC DDDDDDDDD SSSSSSSSS NEGC D,S/# ZCWS 0101101 ZC I CCCC DDDDDDDDD SSSSSSSSS NEGNC D,S/# ZCWS 0101110 ZC I CCCC DDDDDDDDD SSSSSSSSS NEGZ D,S/# ZCWS 0101111 ZC I CCCC DDDDDDDDD SSSSSSSSS NEGNZ D,S/# ZCMS 0110000 ZC I CCCC DDDDDDDDD SSSSSSSSS SETS D,S/# ZCMS 0110001 ZC I CCCC DDDDDDDDD SSSSSSSSS SETD D,S/# ZCMS 0110010 ZC I CCCC DDDDDDDDD SSSSSSSSS SETCOND D,S/# ZCMS 0110011 ZC I CCCC DDDDDDDDD SSSSSSSSS SETINST D,S/# ZCMS 0110100 ZC I CCCC DDDDDDDDD SSSSSSSSS MIN D,S/# ZCMS 0110101 ZC I CCCC DDDDDDDDD SSSSSSSSS MAX D,S/# ZCMS 0110110 ZC I CCCC DDDDDDDDD SSSSSSSSS MINS D,S/# ZCMS 0110111 ZC I CCCC DDDDDDDDD SSSSSSSSS MAXS D,S/# ZCMS 0111000 ZC I CCCC DDDDDDDDD SSSSSSSSS MUL D,S/# ZCMS 0111001 ZC I CCCC DDDDDDDDD SSSSSSSSS MULS D,S/# ZCWS 0111011 ZC I CCCC DDDDDDDDD SSSSSSSSS TOPBIT D,S/# ZCWS 0111100 ZC I CCCC DDDDDDDDD SSSSSSSSS DECOD5 D,S/# ZCWS 0111101 ZC I CCCC DDDDDDDDD SSSSSSSSS ESWAP8 D,S/# ZCWS 0111110 ZC I CCCC DDDDDDDDD SSSSSSSSS SPLITW D,S/# ZCWS 0111111 ZC I CCCC DDDDDDDDD SSSSSSSSS MERGEW D,S/# ZCMS 1001000 ZC I CCCC DDDDDDDDD SSSSSSSSS INCMOD D,S/# ZCMS 1001001 ZC I CCCC DDDDDDDDD SSSSSSSSS DECMOD D,S/# ZCMS 1001011 ZC I CCCC DDDDDDDDD SSSSSSSSS SUBR D,S/# ZCMS 1001110 ZC I CCCC DDDDDDDDD SSSSSSSSS ROLNIB D,S/# ZCMS 1001111 ZC I CCCC DDDDDDDDD SSSSSSSSS ROLBYTE D,S/# --WS 1010xnn n0 I CCCC DDDDDDDDD SSSSSSSSS GETNIB D,S/#,#0..7 --MS 1010xnn n1 I CCCC DDDDDDDDD SSSSSSSSS SETNIB D,S/#,#0..7 --WS 1011xxn n0 I CCCC DDDDDDDDD SSSSSSSSS GETBYTE D,S/#,#0..3 --MS 1011xxn n1 I CCCC DDDDDDDDD SSSSSSSSS SETBYTE D,S/#,#0..3 ZCRS 1000000 ZC I CCCC DDDDDDDDD SSSSSSSSS TESTB D,S/# ZCRS 1000001 ZC I CCCC DDDDDDDDD SSSSSSSSS TESTN D,S/# ZCRS 1000010 ZC I CCCC DDDDDDDDD SSSSSSSSS TEST D,S/# ZCRS 1000011 ZC I CCCC DDDDDDDDD SSSSSSSSS CMP D,S/# ZCRS 1000100 ZC I CCCC DDDDDDDDD SSSSSSSSS CMPX D,S/# ZCRS 1000101 ZC I CCCC DDDDDDDDD SSSSSSSSS CMPS D,S/# ZCRS 1000110 ZC I CCCC DDDDDDDDD SSSSSSSSS CMPSX D,S/# ZCRS 1000111 ZC I CCCC DDDDDDDDD SSSSSSSSS CMPR D,S/# ZCMS 1001010 ZC I CCCC DDDDDDDDD SSSSSSSSS CMPSUB D,S/# ------------------------------------------------------------------------------------------- ZCMS 0001000 ZC I CCCC DDDDDDDDD SSSSSSSSS ISOB D,S/# ZCMS 0001001 ZC I CCCC DDDDDDDDD SSSSSSSSS NOTB D,S/# ZCMS 0001010 ZC I CCCC DDDDDDDDD SSSSSSSSS CLRB D,S/# ZCMS 0001011 ZC I CCCC DDDDDDDDD SSSSSSSSS SETB D,S/# ZCMS 0001100 ZC I CCCC DDDDDDDDD SSSSSSSSS SETBC D,S/# ZCMS 0001101 ZC I CCCC DDDDDDDDD SSSSSSSSS SETBNC D,S/# ZCMS 0001110 ZC I CCCC DDDDDDDDD SSSSSSSSS SETBZ D,S/# ZCMS 0001111 ZC I CCCC DDDDDDDDD SSSSSSSSS SETBNZ D,S/# ------------------------------------------------------------------------------------------- --L- 1111xxx 00 L CCCC DDDDDDDDD xxx000000 OFFP D/# (pin operations that affect DIR and OUT simultaneously) --L- 1111xxx 00 L CCCC DDDDDDDDD xxx000001 NOTP D/# --L- 1111xxx 00 L CCCC DDDDDDDDD xxx000010 CLRP D/# --L- 1111xxx 00 L CCCC DDDDDDDDD xxx000011 SETP D/# --L- 1111xxx 00 L CCCC DDDDDDDDD xxx000100 SETPC D/# --L- 1111xxx 00 L CCCC DDDDDDDDD xxx000101 SETPNC D/# --L- 1111xxx 00 L CCCC DDDDDDDDD xxx000110 SETPZ D/# --L- 1111xxx 00 L CCCC DDDDDDDDD xxx000111 SETPNZ D/# ZCL- 1111xxx ZC L CCCC DDDDDDDDD xxx001000 GETP D/# (pin into !Z/C via WZ/WC) ZCL- 1111xxx ZC L CCCC DDDDDDDDD xxx001001 GETNP D/# (pin into Z/!C via WZ/WC) ------------------------------------------------------------------------------------------- --LS 1100110 0L I CCCC DDDDDDDDD SSSSSSSSS JP D/#,S/@ --LS 1100110 1L I CCCC DDDDDDDDD SSSSSSSSS JPD D/#,S/@ --LS 1100111 0L I CCCC DDDDDDDDD SSSSSSSSS JNP D/#,S/@ --LS 1100111 1L I CCCC DDDDDDDDD SSSSSSSSS JNPD D/#,S/@ ZCMS 1001000 ZC I CCCC DDDDDDDDD SSSSSSSSS DJZ D,S/@ ZCMS 1001001 ZC I CCCC DDDDDDDDD SSSSSSSSS DJNZ D,S/@ ZCRS 1001010 ZC I CCCC DDDDDDDDD SSSSSSSSS TJZ D,S/@ ZCRS 1001011 ZC I CCCC DDDDDDDDD SSSSSSSSS TJNZ D,S/@ --L- 1111xxx 00 L CCCC DDDDDDDDD xxx010100 JMPT0 D/# --L- 1111xxx 00 L CCCC DDDDDDDDD xxx010101 JMPT1 D/# --L- 1111xxx 00 L CCCC DDDDDDDDD xxx010110 JMPT2 D/# --L- 1111xxx 00 L CCCC DDDDDDDDD xxx010111 JMPT3 D/# ZCMS 0111010 ZC I CCCC DDDDDDDDD SSSSSSSSS JMPSW D,S/@ (save Z/C/PC into D, load Z/C/PC from S/#) --R- 1111xxx ZC 0 CCCC DDDDDDDDD xxx110010 JMP D (D[18:17] into Z/C via WZ/WC for JMP..LINK D) ---- 11101xx 00 0 CCCC 0 nnnnnnnnnnnnnnnnn JMP #abs ---- 11101xx 00 0 CCCC 1 nnnnnnnnnnnnnnnnn JMP @rel --R- 1111xxx ZC 0 CCCC DDDDDDDDD xxx110011 CALL D (call using 4-level stack) ---- 11101xx 00 1 CCCC 0 nnnnnnnnnnnnnnnnn CALL #abs ---- 11101xx 00 1 CCCC 1 nnnnnnnnnnnnnnnnn CALL @rel ZC-- 1111xxx ZC 0 CCCC xxxxxxxxx xxx11100x RET (return using 4-level stack) --L- 1111xxx 00 L CCCC DDDDDDDDD xxx011010 PUSH D/# (pushes into 4-level stack) Z-W- 1111xxx Z0 0 CCCC DDDDDDDDD xxx100010 POP D (pops from 4-level stack) --R- 1111xxx ZC 0 CCCC DDDDDDDDD xxx110100 CALLA D (call using PTRA) ---- 11101xx 01 0 CCCC 0 nnnnnnnnnnnnnnnnn CALLA #abs ---- 11101xx 01 0 CCCC 1 nnnnnnnnnnnnnnnnn CALLA @rel ZC-- 1111xxx ZC 0 CCCC xxxxxxxxx xxx111010 RETA (return using PTRA) PUSHA D/# (alias for WRLONG D/#,PTRA++) POPA (alias for RDLONG D,--PTRA) --R- 1111xxx ZC 0 CCCC DDDDDDDDD xxx110101 CALLB D (call using PTRB) ---- 11101xx 01 1 CCCC 0 nnnnnnnnnnnnnnnnn CALLB #abs ---- 11101xx 01 1 CCCC 1 nnnnnnnnnnnnnnnnn CALLB @rel ZC-- 1111xxx ZC 0 CCCC xxxxxxxxx xxx111011 RETB (return using PTRB) PUSHB D/# (alias for WRLONG D/#,PTRB++) POPB (alias for RDLONG D,--PTRB) --R- wr 1111xxx ZC 0 CCCC DDDDDDDDD xxx110110 LINK D (jump and write {0000000000000,Z,C,PC[16:0]} to $1EF) ---- wr 11101xx 10 0 CCCC 0 nnnnnnnnnnnnnnnnn LINK #abs (jump and write {0000000000000,Z,C,PC[16:0]} to $1EF) ---- wr 11101xx 10 0 CCCC 1 nnnnnnnnnnnnnnnnn LINK @rel (jump and write {0000000000000,Z,C,PC[16:0]} to $1EF) ---- wr 11101xx 10 1 CCCC 0 nnnnnnnnnnnnnnnnn LOCINST #abs (write 17-bit instruction address to $1EF) ---- wr 11101xx 10 1 CCCC 1 nnnnnnnnnnnnnnnnn LOCINST @rel (write 17-bit instruction address to $1EF) --R- 1111xxx 00 0 CCCC DDDDDDDDD xxx110000 LOCPTRA D (PTRA = {D[16:0],00}) ---- 11101xx 11 0 CCCC 0 nnnnnnnnnnnnnnnnn LOCPTRA #abs (write 17-bit instruction address << 2 to PTRA) ---- 11101xx 11 0 CCCC 1 nnnnnnnnnnnnnnnnn LOCPTRA @rel (write 17-bit instruction address << 2 to PTRA) --R- 1111xxx 00 0 CCCC DDDDDDDDD xxx110001 LOCPTRB D (PTRB = {D[16:0],00}) ---- 11101xx 11 1 CCCC 0 nnnnnnnnnnnnnnnnn LOCPTRB #abs (write 17-bit instruction address << 2 to PTRB) ---- 11101xx 11 1 CCCC 1 nnnnnnnnnnnnnnnnn LOCPTRB @rel (write 17-bit instruction address << 2 to PTRB) ------------------------------------------------------------------------------------------- --L- 1111xxx 00 L CCCC DDDDDDDDD xxx011000 WAIT D/# (waits 1+ clocks, 0 same as 1) ZCMS 1001100 ZC I CCCC DDDDDDDDD SSSSSSSSS WAITCNT D,S/# --LS 1100010 0L I CCCC DDDDDDDDD SSSSSSSSS WAITPAE D/#,S/# (waits for INA) --LS 1100010 1L I CCCC DDDDDDDDD SSSSSSSSS WAITPAN D/#,S/# (waits for INA) --LS 1100011 0L I CCCC DDDDDDDDD SSSSSSSSS WAITPBE D/#,S/# (waits for INB) --LS 1100011 1L I CCCC DDDDDDDDD SSSSSSSSS WAITPBN D/#,S/# (waits for INB) --L- 1111xxx 00 L CCCC DDDDDDDDD xxx001010 WAITPR D/# (waits for pos edge on pin) --L- 1111xxx 00 L CCCC DDDDDDDDD xxx001011 WAITPF D/# (waits for neg edge on pin) --L- 1111xxx 00 L CCCC DDDDDDDDD xxx001100 WAITPX D/# (waits for any edge on pin) --LS 1101001 0L I CCCC DDDDDDDDD SSSSSSSSS WAITVID D/#,S/# (waits for vid) ------------------------------------------------------------------------------------------- --L- 1111xxx 00 L CCCC DDDDDDDDD xxx001110 SETPTRA D/# --L- 1111xxx 00 L CCCC DDDDDDDDD xxx001111 SETPTRB D/# Z-W- 1111xxx Z0 0 CCCC DDDDDDDDD xxx100000 GETPTRA D Z-W- 1111xxx Z0 0 CCCC DDDDDDDDD xxx100001 GETPTRB D --L- 1111xxx 00 L CCCC DDDDDDDDD xxx010000 SETINDA D/# (set INDA/INDB, INDA/INDB increment on each use) --L- 1111xxx 00 L CCCC DDDDDDDDD xxx010001 SETINDB D/# --LS 1101000 0L I CCCC DDDDDDDDD SSSSSSSSS SETINDS D/#,S/# --L- 1111xxx 00 L CCCC DDDDDDDDD xxx010010 ADJINDA D/# (adjust INDA/INDB by adding value) --L- 1111xxx 00 L CCCC DDDDDDDDD xxx010011 ADJINDB D/# --LS 1101000 1L I CCCC DDDDDDDDD SSSSSSSSS ADJINDS D/#,S/# --L- 1111xxx 00 L CCCC DDDDDDDDD xxx001101 SETTASK D/# --L- 1111xxx 00 L CCCC DDDDDDDDD xxx011001 SETVID D/# -------------------------------------------------------------------------------------------- --LS 1100100 0L I CCCC DDDDDDDDD SSSSSSSSS MSGDIRA D/#,S/# --LS 1100100 1L I CCCC DDDDDDDDD SSSSSSSSS MSGDIRB D/#,S/# --LS 1100101 0L I CCCC DDDDDDDDD SSSSSSSSS MSGOUTA D/#,S/# --LS 1100101 1L I CCCC DDDDDDDDD SSSSSSSSS MSGOUTB D/#,S/# ZCWS 1001100 ZC I CCCC DDDDDDDDD SSSSSSSSS MSGINA D,S/# (waits up to 64 clocks to receive 010_data32 message on INA, C=timeout) ZCWS 1001101 ZC I CCCC DDDDDDDDD SSSSSSSSS MSGINB D,S/# (waits up to 64 clocks to receive 010_data32 message on INB, C=timeout) ------------------------------------------------------------------------------------------- ---- 0000000 00 0 0000 000000000 000000000 NOP ZCWS 0000111 ZC 1 CCCC DDDDDDDDD SSSSSSSSS SYSOP D,# (waits for hub, # determines four write-long enables) --LS 1101001 1L I CCCC DDDDDDDDD SSSSSSSSS REP D/#,S/# ---- 11100xx x0 n nnnn nnnnnnnnn nnnnnnnnn AUGS #23bits (appends n to upper bits of next immediate S in same task) ---- 11100xx x1 n nnnn nnnnnnnnn nnnnnnnnn AUGD #23bits (appends n to upper bits of next immediate D in same task) --------------------------------------------------------------------------------------------IIRC Chip is going to add the SETZC D/#, #0..32 'position to put D[nn] into Z & C (b1=Z, b0=C if #0)Postedit: See the first post for the latest update !!!
My question was that as their are no delayed instructions, the JPD and JPND are invalid now.
Another query on LINK, In P2(is that called P3 now?) the return address was saved to COG address 0.
Cheers
Brian
The LINK has the notation that the return address is stored to cog $1EF.
Do you know what the register layout is in $1Fx ?
On LINK, thanks I missed that note.
When it comes to naming op codes I believe that it is better to have individual names for functions that a reader can spot and go "THAT looks like what I want".
If you cram a bunch of modes into one op code (name) then it can make it very hard for someone new to find what they are looking for.
I have worked on so many micros, sometimes I draw a blank for a mnemonic and I have to look thru a list. Oh, and I might be having a "senior moment"
So THAT is what I am having when I constantly have to go back and relocate that instruction that I know I just used the other day... LOL.
Yes I agree common functions need common grouped naming formats so that it is easy to scan a list and see what is there.
I drove my self CRAZY for weeks when I started with the P1 looking for the 'SETBIT' function command... Kept thinking I must be missing something somewhere and that was why I could not find it...
Because there is no pipeline in this new chip, there are no delayed branches. So, all those -D branches are gone.
I put the PICKZC D/#,S/# instruction in, since it provides the most flexibility.
Yes, I don't know what I was thinking. JPD and JNPD won't exist.