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The New 16-Cog, 512KB, 64 analog I/O Propeller Chip - Page 14 — Parallax Forums

The New 16-Cog, 512KB, 64 analog I/O Propeller Chip

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Comments

  • ctwardellctwardell Posts: 1,716
    edited 2014-04-09 04:47
    cgracey wrote: »
    I've thought about this, too, but lots of nets between all cogs, would take a lot of power. Between adjacent cogs, maybe not so much - if they actually wound up adjacent in the layout.

    I will increase the locks to 32 in the hub.

    Thanks Chip.
  • cgraceycgracey Posts: 14,133
    edited 2014-04-09 04:58
    Heater. wrote: »
    Thanks Chip,

    Shame, it's just a gnats whisker too big to fit on a module with a pin out like so :


    Let just call it the Circus chip. The hub can be renamed "The Big Top" and the cogs can be "Trailers" occupied by short, fat programs called "Carnies". When multitasking is on, they become "Fun Houses". All the new pipelined math circuits can be collectively called "Midway". The 512-long program memory can be featured in the "Freak Show". Wait, wait, that's all politically incorrect, nowadays. We need a bold, new name that commands reverence: "Sustainable Diversity Cluster". It thrives in an "Eco System" of mobile apps and exceptionally neutral people who were born about about five minutes ago.
  • mindrobotsmindrobots Posts: 6,506
    edited 2014-04-09 05:01
    cgracey wrote: »
    Let just call it the Circus chip. The hub can be renamed "The Big Top" and the cogs can be "Trailers" occupied by short, fat programs called "Carnies". When multitasking is on, they become "Fun Houses". All the new pipelined math circuits can be collectively called "Midway". The 512-long program memory can be featured in the "Freak Show". Wait, wait, that's all politically incorrect, nowadays. We need a bold, new name that commands reverence: "Sustainable Diversity Cluster". It thrives in an "Eco System" of mobile apps and exceptionally neutral people who were born about about five minutes ago.

    ...with Smart Pins(tm)!! :smile:
  • cgraceycgracey Posts: 14,133
    edited 2014-04-09 05:07
    Okay. I've got the new instruction set arranged. It's not final, but it tells what the cog does:
    ZCDS (for D column: W=write, M=modify, R=read, L=read/immediate)
    ----------------------------------------------------------------------------------------------------------------------
    
    ZCWS		0000000 ZC 1 CCCC DDDDDDDDD SSSSSSSSS		RDBYTE	D,PTRA/PTRB		(waits for hub)
    ZCWS		0000001 ZC 1 CCCC DDDDDDDDD SSSSSSSSS		RDBYTEC	D,PTRA/PTRB		(waits for hub if dcache miss)
    ZCWS		0000010 ZC 1 CCCC DDDDDDDDD SSSSSSSSS		RDWORD	D,PTRA/PTRB		(waits for hub)
    ZCWS		0000011 ZC 1 CCCC DDDDDDDDD SSSSSSSSS		RDWORDC	D,PTRA/PTRB		(waits for hub if dcache miss)
    ZCWS		0000100 ZC 1 CCCC DDDDDDDDD SSSSSSSSS		RDLONG	D,PTRA/PTRB		(waits for hub)
    ZCWS		0000101 ZC 1 CCCC DDDDDDDDD SSSSSSSSS		RDLONGC	D,PTRA/PTRB		(waits for hub if dcache miss)
    ZCWS		0000110 ZC 1 CCCC DDDDDDDDD SSSSSSSSS		RDQUAD	D,PTRA/PTRB		(waits for hub)
    ZCWS		0000111 ZC 1 CCCC DDDDDDDDD SSSSSSSSS		SYSOP	D,#			(waits for hub, # determines four write-long enables)
    
    ZCMS		0001000 ZC I CCCC DDDDDDDDD SSSSSSSSS		ISOB	D,S/#
    ZCMS		0001001 ZC I CCCC DDDDDDDDD SSSSSSSSS		NOTB	D,S/#
    ZCMS		0001010 ZC I CCCC DDDDDDDDD SSSSSSSSS		CLRB	D,S/#
    ZCMS		0001011 ZC I CCCC DDDDDDDDD SSSSSSSSS		SETB	D,S/#
    ZCMS		0001100 ZC I CCCC DDDDDDDDD SSSSSSSSS		SETBC	D,S/#
    ZCMS		0001101 ZC I CCCC DDDDDDDDD SSSSSSSSS		SETBNC	D,S/#
    ZCMS		0001110 ZC I CCCC DDDDDDDDD SSSSSSSSS		SETBZ	D,S/#
    ZCMS		0001111 ZC I CCCC DDDDDDDDD SSSSSSSSS		SETBNZ	D,S/#
    
    ZCMS		0010000 ZC I CCCC DDDDDDDDD SSSSSSSSS		ROR	D,S/#
    ZCMS		0010001 ZC I CCCC DDDDDDDDD SSSSSSSSS		ROL	D,S/#
    ZCMS		0010010 ZC I CCCC DDDDDDDDD SSSSSSSSS		SHR	D,S/#
    ZCMS		0010011 ZC I CCCC DDDDDDDDD SSSSSSSSS		SHL	D,S/#
    ZCMS		0010100 ZC I CCCC DDDDDDDDD SSSSSSSSS		RCR	D,S/#
    ZCMS		0010101 ZC I CCCC DDDDDDDDD SSSSSSSSS		RCL	D,S/#
    ZCMS		0010110 ZC I CCCC DDDDDDDDD SSSSSSSSS		SAR	D,S/#
    ZCMS		0010111 ZC I CCCC DDDDDDDDD SSSSSSSSS		REV	D,S/#
    
    ZCMS		0011000 ZC I CCCC DDDDDDDDD SSSSSSSSS		ANDN	D,S/#
    ZCMS		0011001 ZC I CCCC DDDDDDDDD SSSSSSSSS		AND	D,S/#
    ZCMS		0011010 ZC I CCCC DDDDDDDDD SSSSSSSSS		OR	D,S/#
    ZCMS		0011011 ZC I CCCC DDDDDDDDD SSSSSSSSS		XOR	D,S/#
    ZCMS		0011100 ZC I CCCC DDDDDDDDD SSSSSSSSS		MUXC	D,S/#
    ZCMS		0011101 ZC I CCCC DDDDDDDDD SSSSSSSSS		MUXNC	D,S/#
    ZCMS		0011110 ZC I CCCC DDDDDDDDD SSSSSSSSS		MUXZ	D,S/#
    ZCMS		0011111 ZC I CCCC DDDDDDDDD SSSSSSSSS		MUXNZ	D,S/#
    
    ZCMS		0100000 ZC I CCCC DDDDDDDDD SSSSSSSSS		ADD	D,S/#
    ZCMS		0100001 ZC I CCCC DDDDDDDDD SSSSSSSSS		SUB	D,S/#
    ZCMS		0100010 ZC I CCCC DDDDDDDDD SSSSSSSSS		ADDX	D,S/#
    ZCMS		0100011 ZC I CCCC DDDDDDDDD SSSSSSSSS		SUBX	D,S/#
    ZCMS		0100100 ZC I CCCC DDDDDDDDD SSSSSSSSS		SUMC	D,S/#
    ZCMS		0100101 ZC I CCCC DDDDDDDDD SSSSSSSSS		SUMNC	D,S/#
    ZCMS		0100110 ZC I CCCC DDDDDDDDD SSSSSSSSS		SUMZ	D,S/#
    ZCMS		0100111 ZC I CCCC DDDDDDDDD SSSSSSSSS		SUMNZ	D,S/#
    
    ZCWS		0101000 ZC I CCCC DDDDDDDDD SSSSSSSSS		MOV	D,S/#
    ZCWS		0101001 ZC I CCCC DDDDDDDDD SSSSSSSSS		NOT	D,S/#
    ZCWS		0101010 ZC I CCCC DDDDDDDDD SSSSSSSSS		ABS	D,S/#
    ZCWS		0101011 ZC I CCCC DDDDDDDDD SSSSSSSSS		NEG	D,S/#
    ZCWS		0101100 ZC I CCCC DDDDDDDDD SSSSSSSSS		NEGC	D,S/#
    ZCWS		0101101 ZC I CCCC DDDDDDDDD SSSSSSSSS		NEGNC	D,S/#
    ZCWS		0101110 ZC I CCCC DDDDDDDDD SSSSSSSSS		NEGZ	D,S/#
    ZCWS		0101111 ZC I CCCC DDDDDDDDD SSSSSSSSS		NEGNZ	D,S/#
    
    ZCMS		0110000 ZC I CCCC DDDDDDDDD SSSSSSSSS		SETS	D,S/#
    ZCMS		0110001 ZC I CCCC DDDDDDDDD SSSSSSSSS		SETD	D,S/#
    ZCMS		0110010 ZC I CCCC DDDDDDDDD SSSSSSSSS		SETCOND	D,S/#
    ZCMS		0110011 ZC I CCCC DDDDDDDDD SSSSSSSSS		SETINST	D,S/#
    ZCMS		0110100 ZC I CCCC DDDDDDDDD SSSSSSSSS		MIN	D,S/#
    ZCMS		0110101 ZC I CCCC DDDDDDDDD SSSSSSSSS		MAX	D,S/#
    ZCMS		0110110 ZC I CCCC DDDDDDDDD SSSSSSSSS		MINS	D,S/#
    ZCMS		0110111 ZC I CCCC DDDDDDDDD SSSSSSSSS		MAXS	D,S/#
    
    ZCMS		0111000 ZC I CCCC DDDDDDDDD SSSSSSSSS		MUL	D,S/#
    ZCMS		0111001 ZC I CCCC DDDDDDDDD SSSSSSSSS		MULS	D,S/#
    ZCMS		0111010 ZC I CCCC DDDDDDDDD SSSSSSSSS		JMPSW	D,S/@			(save Z/C/PC into D, load Z/C/PC from S/#)
    ZCWS		0111011 ZC I CCCC DDDDDDDDD SSSSSSSSS		TOPBIT	D,S/#
    ZCWS		0111100 ZC I CCCC DDDDDDDDD SSSSSSSSS		DECOD5	D,S/#
    ZCWS		0111101 ZC I CCCC DDDDDDDDD SSSSSSSSS		ESWAP8	D,S/#
    ZCWS		0111110 ZC I CCCC DDDDDDDDD SSSSSSSSS		SPLITW	D,S/#
    ZCWS		0111111 ZC I CCCC DDDDDDDDD SSSSSSSSS		MERGEW	D,S/#
    
    ZCRS		1000000 ZC I CCCC DDDDDDDDD SSSSSSSSS		TESTB	D,S/#
    ZCRS		1000001 ZC I CCCC DDDDDDDDD SSSSSSSSS		TESTN	D,S/#
    ZCRS		1000010 ZC I CCCC DDDDDDDDD SSSSSSSSS		TEST	D,S/#
    ZCRS		1000011 ZC I CCCC DDDDDDDDD SSSSSSSSS		CMP	D,S/#
    ZCRS		1000100 ZC I CCCC DDDDDDDDD SSSSSSSSS		CMPX	D,S/#
    ZCRS		1000101 ZC I CCCC DDDDDDDDD SSSSSSSSS		CMPS	D,S/#
    ZCRS		1000110 ZC I CCCC DDDDDDDDD SSSSSSSSS		CMPSX	D,S/#
    ZCRS		1000111 ZC I CCCC DDDDDDDDD SSSSSSSSS		CMPR	D,S/#
    
    ZCMS		1001000 ZC I CCCC DDDDDDDDD SSSSSSSSS		INCMOD	D,S/#
    ZCMS		1001001 ZC I CCCC DDDDDDDDD SSSSSSSSS		DECMOD	D,S/#
    ZCMS		1001010 ZC I CCCC DDDDDDDDD SSSSSSSSS		CMPSUB	D,S/#
    ZCMS		1001011 ZC I CCCC DDDDDDDDD SSSSSSSSS		SUBR	D,S/#
    
    ZCWS		1001100 ZC I CCCC DDDDDDDDD SSSSSSSSS		MSGINA	D,S/#			(waits up to 64 clocks to receive %010_data32 message on INA, C=timeout)
    ZCWS		1001101 ZC I CCCC DDDDDDDDD SSSSSSSSS		MSGINB	D,S/#			(waits up to 64 clocks to receive %010_data32 message on INB, C=timeout)
    ZCMS		1001110 ZC I CCCC DDDDDDDDD SSSSSSSSS		ROLNIB	D,S/#
    ZCMS		1001111 ZC I CCCC DDDDDDDDD SSSSSSSSS		ROLBYTE	D,S/#
    
    ZCMS		1001000 ZC I CCCC DDDDDDDDD SSSSSSSSS		DJZ	D,S/@
    ZCMS		1001001 ZC I CCCC DDDDDDDDD SSSSSSSSS		DJNZ	D,S/@
    ZCRS		1001010 ZC I CCCC DDDDDDDDD SSSSSSSSS		TJZ	D,S/@
    ZCRS		1001011 ZC I CCCC DDDDDDDDD SSSSSSSSS		TJNZ	D,S/@
    
    ZCMS		1001100 ZC I CCCC DDDDDDDDD SSSSSSSSS		WAITCNT	D,S/#
    
    --WS		1010xnn n0 I CCCC DDDDDDDDD SSSSSSSSS		GETNIB	D,S/#,#0..7
    --MS		1010xnn n1 I CCCC DDDDDDDDD SSSSSSSSS		SETNIB	D,S/#,#0..7
    --WS		1011xxn n0 I CCCC DDDDDDDDD SSSSSSSSS		GETBYTE	D,S/#,#0..3
    --MS		1011xxn n1 I CCCC DDDDDDDDD SSSSSSSSS		SETBYTE	D,S/#,#0..3
    
    --LS		1100000 0L 1 CCCC DDDDDDDDD SSSSSSSSS		WRBYTE	D/#,PTRA/PTRB		(waits for hub)
    --LS		1100000 1L 1 CCCC DDDDDDDDD SSSSSSSSS		WRWORD	D/#,PTRA/PTRB		(waits for hub)
    --LS		1100001 0L 1 CCCC DDDDDDDDD SSSSSSSSS		WRLONG	D/#,PTRA/PTRB		(waits for hub)
    --LS		1100001 1L 1 CCCC DDDDDDDDD SSSSSSSSS		WRQUAD	D/#,PTRA/PTRB		(waits for hub, zero-extends #)
    
    --LS		1100010 0L I CCCC DDDDDDDDD SSSSSSSSS		WAITPAE	D/#,S/#			(waits for INA)
    --LS		1100010 1L I CCCC DDDDDDDDD SSSSSSSSS		WAITPAN	D/#,S/#			(waits for INA)
    --LS		1100011 0L I CCCC DDDDDDDDD SSSSSSSSS		WAITPBE	D/#,S/#			(waits for INB)
    --LS		1100011 1L I CCCC DDDDDDDDD SSSSSSSSS		WAITPBN	D/#,S/#			(waits for INB)
    
    --LS		1100100 0L I CCCC DDDDDDDDD SSSSSSSSS		MSGDIRA	D/#,S/#
    --LS		1100100 1L I CCCC DDDDDDDDD SSSSSSSSS		MSGDIRB	D/#,S/#
    --LS		1100101 0L I CCCC DDDDDDDDD SSSSSSSSS		MSGOUTA	D/#,S/#
    --LS		1100101 1L I CCCC DDDDDDDDD SSSSSSSSS		MSGOUTB	D/#,S/#
    
    --LS		1100110 0L I CCCC DDDDDDDDD SSSSSSSSS		JP	D/#,S/@
    --LS		1100110 1L I CCCC DDDDDDDDD SSSSSSSSS		JPD	D/#,S/@
    --LS		1100111 0L I CCCC DDDDDDDDD SSSSSSSSS		JNP	D/#,S/@
    --LS		1100111 1L I CCCC DDDDDDDDD SSSSSSSSS		JNPD	D/#,S/@
    
    --LS		1101000 0L I CCCC DDDDDDDDD SSSSSSSSS		SETINDS	D/#,S/#
    --LS		1101000 1L I CCCC DDDDDDDDD SSSSSSSSS		ADJINDS	D/#,S/#
    --LS		1101001 0L I CCCC DDDDDDDDD SSSSSSSSS		WAITVID	D/#,S/#			(waits for vid)
    --LS		1101001 1L I CCCC DDDDDDDDD SSSSSSSSS		REP	D/#,S/#
    
    ----		11100xx x0 n nnnn nnnnnnnnn nnnnnnnnn		AUGS	#23bits			(appends n to upper bits of next immediate S in same task)
    ----		11100xx x1 n nnnn nnnnnnnnn nnnnnnnnn		AUGD	#23bits			(appends n to upper bits of next immediate D in same task)
    
    ----		11101xx 00 0 CCCC 0 nnnnnnnnnnnnnnnnn		JMP	#abs
    ----		11101xx 00 0 CCCC 1 nnnnnnnnnnnnnnnnn		JMP	@rel
    ----		11101xx 00 1 CCCC 0 nnnnnnnnnnnnnnnnn		CALL	#abs
    ----		11101xx 00 1 CCCC 1 nnnnnnnnnnnnnnnnn		CALL	@rel
    ----		11101xx 01 0 CCCC 0 nnnnnnnnnnnnnnnnn		CALLA	#abs
    ----		11101xx 01 0 CCCC 1 nnnnnnnnnnnnnnnnn		CALLA	@rel
    ----		11101xx 01 1 CCCC 0 nnnnnnnnnnnnnnnnn		CALLB	#abs
    ----		11101xx 01 1 CCCC 1 nnnnnnnnnnnnnnnnn		CALLB	@rel
    ---- wr		11101xx 10 0 CCCC 0 nnnnnnnnnnnnnnnnn		LINK	#abs			(jump and write {%0000000000000,Z,C,PC[16:0]} to $1EF)
    ---- wr		11101xx 10 0 CCCC 1 nnnnnnnnnnnnnnnnn		LINK	@rel			(jump and write {%0000000000000,Z,C,PC[16:0]} to $1EF)
    ---- wr		11101xx 10 1 CCCC 0 nnnnnnnnnnnnnnnnn		LOCINST	#abs			(write 17-bit instruction address to $1EF)
    ---- wr		11101xx 10 1 CCCC 1 nnnnnnnnnnnnnnnnn		LOCINST	@rel			(write 17-bit instruction address to $1EF)
    ----		11101xx 11 0 CCCC 0 nnnnnnnnnnnnnnnnn		LOCPTRA	#abs			(write 17-bit instruction address << 2 to PTRA)
    ----		11101xx 11 0 CCCC 1 nnnnnnnnnnnnnnnnn		LOCPTRA	@rel			(write 17-bit instruction address << 2 to PTRA)
    ----		11101xx 11 1 CCCC 0 nnnnnnnnnnnnnnnnn		LOCPTRB	#abs			(write 17-bit instruction address << 2 to PTRB)
    ----		11101xx 11 1 CCCC 1 nnnnnnnnnnnnnnnnn		LOCPTRB	@rel			(write 17-bit instruction address << 2 to PTRB)
    
    --L-		1111xxx 00 L CCCC DDDDDDDDD xxx000000		OFFP	D/#			(pin operations that affect DIR and OUT simultaneously)
    --L-		1111xxx 00 L CCCC DDDDDDDDD xxx000001		NOTP	D/#
    --L-		1111xxx 00 L CCCC DDDDDDDDD xxx000010		CLRP	D/#
    --L-		1111xxx 00 L CCCC DDDDDDDDD xxx000011		SETP	D/#
    --L-		1111xxx 00 L CCCC DDDDDDDDD xxx000100		SETPC	D/#
    --L-		1111xxx 00 L CCCC DDDDDDDDD xxx000101		SETPNC	D/#
    --L-		1111xxx 00 L CCCC DDDDDDDDD xxx000110		SETPZ	D/#
    --L-		1111xxx 00 L CCCC DDDDDDDDD xxx000111		SETPNZ	D/#
    
    ZCL-		1111xxx ZC L CCCC DDDDDDDDD xxx001000		GETP	D/#			(pin into !Z/C via WZ/WC)
    ZCL-		1111xxx ZC L CCCC DDDDDDDDD xxx001001		GETNP	D/#			(pin into Z/!C via WZ/WC)
    --L-		1111xxx 00 L CCCC DDDDDDDDD xxx001010		WAITPR	D/#			(waits for pos edge on pin)
    --L-		1111xxx 00 L CCCC DDDDDDDDD xxx001011		WAITPF	D/#			(waits for neg edge on pin)
    --L-		1111xxx 00 L CCCC DDDDDDDDD xxx001100		WAITPX	D/#			(waits for any edge on pin)
    --L-		1111xxx 00 L CCCC DDDDDDDDD xxx001101		SETTASK	D/#
    --L-		1111xxx 00 L CCCC DDDDDDDDD xxx001110		SETPTRA	D/#
    --L-		1111xxx 00 L CCCC DDDDDDDDD xxx001111		SETPTRB	D/#
    --L-		1111xxx 00 L CCCC DDDDDDDDD xxx010000		SETINDA	D/#			(set INDA/INDB, INDA/INDB increment on each use)
    --L-		1111xxx 00 L CCCC DDDDDDDDD xxx010001		SETINDB	D/#
    --L-		1111xxx 00 L CCCC DDDDDDDDD xxx010010		ADJINDA	D/#			(adjust INDA/INDB by adding value)
    --L-		1111xxx 00 L CCCC DDDDDDDDD xxx010011		ADJINDB	D/#
    --L-		1111xxx 00 L CCCC DDDDDDDDD xxx010100		JMPT0	D/#
    --L-		1111xxx 00 L CCCC DDDDDDDDD xxx010101		JMPT1	D/#
    --L-		1111xxx 00 L CCCC DDDDDDDDD xxx010110		JMPT2	D/#
    --L-		1111xxx 00 L CCCC DDDDDDDDD xxx010111		JMPT3	D/#
    --L-		1111xxx 00 L CCCC DDDDDDDDD xxx011000		WAIT	D/#			(waits 1+ clocks, 0 same as 1)
    --L-		1111xxx 00 L CCCC DDDDDDDDD xxx011001		SETVID	D/#
    --L-		1111xxx 00 L CCCC DDDDDDDDD xxx011010		PUSH	D/#			(pushes into 4-level stack)
    
    Z-W-		1111xxx Z0 0 CCCC DDDDDDDDD xxx100000		GETPTRA	D
    Z-W-		1111xxx Z0 0 CCCC DDDDDDDDD xxx100001		GETPTRB	D
    Z-W-		1111xxx Z0 0 CCCC DDDDDDDDD xxx100010		POP	D			(pops from 4-level stack)
    
    --R-		1111xxx 00 0 CCCC DDDDDDDDD xxx110000		LOCPTRA	D			(PTRA = {D[16:0],%00})
    --R-		1111xxx 00 0 CCCC DDDDDDDDD xxx110001		LOCPTRB	D			(PTRB = {D[16:0],%00})
    --R-		1111xxx ZC 0 CCCC DDDDDDDDD xxx110010		JMP	D			(D[18:17] into Z/C via WZ/WC for JMP..LINK D)
    --R-		1111xxx ZC 0 CCCC DDDDDDDDD xxx110011		CALL	D			(call using 4-level stack)
    --R-		1111xxx ZC 0 CCCC DDDDDDDDD xxx110100		CALLA	D			(call using PTRA)
    --R-		1111xxx ZC 0 CCCC DDDDDDDDD xxx110101		CALLB	D			(call using PTRB)
    --R- wr		1111xxx ZC 0 CCCC DDDDDDDDD xxx110110		LINK	D			(jump and write {%0000000000000,Z,C,PC[16:0]} to $1EF)
    
    ZC--		1111xxx ZC 0 CCCC xxxxxxxxx xxx11100x		RET				(return using 4-level stack)
    ZC--		1111xxx ZC 0 CCCC xxxxxxxxx xxx111010		RETA				(return using PTRA)
    ZC--		1111xxx ZC 0 CCCC xxxxxxxxx xxx111011		RETB				(return using PTRB)
    ----		1111xxx 00 0 CCCC xxxxxxxxx xxx111100		DCACHEX				(invalidate data cache)
    ----		1111xxx 00 0 CCCC xxxxxxxxx xxx111101		ICACHEX				(invalidate instruction cache)
    
    ----		0000000 00 0 0000 000000000 000000000		NOP
    
    			 					PUSHA	D/# 			(alias for WRLONG D/#,PTRA++)
    								PUSHB	D/# 			(alias for WRLONG D/#,PTRB++)
    								POPA	 			(alias for RDLONG D,--PTRA)
    								POPB	 			(alias for RDLONG D,--PTRB)
    x = don't care, use 0
    ---------------------------------------------------------------------------------------------------------------------
    


    I think this will provide us with a nice programming platform, while keeping pretty skinny. This is like a non-fat version of Prop2.

    Does anyone see any pitfalls, or something that needs to be in there, but isn't? Or something that IS in there that shouldn't be?
  • Heater.Heater. Posts: 21,230
    edited 2014-04-09 05:13
    Brian,
    that's a 64-pin 0.9 package right? So 22.86mm between rows of pins?
    Yes, you are right. I had quickly checked my 68000 manual and got the width of a 48 pin DIP, only 15.24mm

    Great, I can get on with that 68000 emulator now and get it into the correct size!
  • Heater.Heater. Posts: 21,230
    edited 2014-04-09 05:15
    Chip,
    Let just call it the Circus chip....
    Let's not. There are too many clowns in this ring already :)
  • Kerry SKerry S Posts: 163
    edited 2014-04-09 05:25
    Cluso99 wrote: »
    I absolutely agree, Core(s) it should be!
    It will then come up in search entries and be compared with other multi-core chips. We are seeing numerous ARM multi-cores appearing. Microcontrollers will no doubt follow, and then Parallax is clearly in the lead. And you will get a lot of free press because they understand what cores is.

    Next, I think the cog memory should be Core RAM Registers/Memory and described as Private Core RAM Memory 2KB (496 x 32bit longs with 128bit wide access to Common Memory).

    And lastly, the hub memory should be described as Common RAM Memory 512KB (byte/word/long/quadlong), shared between all Cores, and usable as expanded instruction and/or memory space.

    We have to ditch our favourite words to embrace the market that should be able to understand these simpler definitions.

    Cluso is right on the MONEY here.

    You NEED to use common terms. A big reason for that is SEARCHING. Your custom descriptors cause you to fail to come up, or rank low, in a lot of common search terms.

    Like others here I have found it frustrating to find the Prop on retail sites when I KNEW they were there. All because you don't show up in the search functions.

    Example: Go to mouser and enter multi-core in the search. You get 33 results, not one Prop reference. Yet they sell them! You have to search for 'propeller' to find them.

    Why? Because searching is automated based on database field and pattern matching.

    Go to digikey and search 'core'. Select Integrated Circuits (ICs) > Embedded - Microcontrollers. Then select '32-Bit 8-Core' in the Core Size filter. You get 31 XMOS chips, no propeller! Yet they too sell them!

    You are losing out on potential sales because your terms don't match industry standards and you are getting lost in searches.
  • cgraceycgracey Posts: 14,133
    edited 2014-04-09 05:31
    Kerry S wrote: »
    Cluso is right on the MONEY here.

    You NEED to use common terms. A big reason for that is SEARCHING. Your custom descriptors cause you to fail to come up, or rank low, in a lot of common search terms.

    Like others here I have found it frustrating to find the Prop on retail sites when I KNEW they were there. All because you don't show up in the search functions.

    Example: Go to mouser and enter multi-core in the search. You get 33 results, not one Prop reference. Yet they sell them! You have to search for 'propeller' to find them.

    Why? Because searching is automated based on database field and pattern matching.

    Go to digikey and search 'core'. Select Integrated Circuits (ICs) > Embedded - Microcontrollers. Then select '32-Bit 8-Core' in the Core Size filter. You get 31 XMOS chips, no propeller! Yet they too sell them!

    You are losing out on potential sales because your terms don't match industry standards and you are getting lost in searches.


    Ken needs to see this.
  • T ChapT Chap Posts: 4,208
    edited 2014-04-09 05:37
    Is a .65mm pitch package a possibility?
  • Heater.Heater. Posts: 21,230
    edited 2014-04-09 05:40
    Chip,

    Ken really needs to see that.

    I have been saying this for a long time now, see my recurring story about the ELFA distributor a few posts back in this thread today.

    Kerry S has put it much better than I did.

    I believe this is keeping the Propeller off the radar for many engineers.
  • ozpropdevozpropdev Posts: 2,791
    edited 2014-04-09 05:51
    Chip

    Had a quick look
    COGRUN,COGINIT?
    Maybe a TASKID instruction

    Looks good! :)
    Brian

    Edit: PASSCNT?
  • Alex.StanfieldAlex.Stanfield Posts: 198
    edited 2014-04-09 05:53
    T Chap wrote: »
    Snow Leopard, Mountain Lion, Mavericks

    Numbers are boring and don't "emote"

    HyperProp...

    I'm not sure about that. Is "Snow Leopard" more than "Maverick" ??

    People love to compare for whatever reason. The following may not be a fair analogy but even BMW has its "3 series", "5 series", an so on which imply superior performance. Without a clear orientation you need additional support information to compare or people will just look at the price and guess.

    Alex
  • cgraceycgracey Posts: 14,133
    edited 2014-04-09 06:03
    Heater. wrote: »
    Chip,

    Ken really needs to see that.

    I have been saying this for a long time now, see my recurring story about the ELFA distributor a few posts back in this thread today.

    Kerry S has put it much better than I did.

    I believe this is keeping the Propeller off the radar for many engineers.


    I think you are right, and I read your post about ELFA. I've noticed the same thing when I've bothered to search on Digi-Key or Mouser. It always makes me wince when I see stuff like that. But, you know, I always imagined there wasn't much we could do about it, because Parallax doesn't "pay to play" all the industry marketing games, and we are not favored by the system, so to speak.

    There was some multi-core processing conference that we were polled to speak at, recently. They asked for submissions on ideas for talks, so we put something together and sent it to them, figuring it wouldn't hurt to speak about the Propeller at some conference. Well, they got back to us and said that the thing was filling up very quickly with 700 registered attendees and speaking spots were filling up fast, too, but there was some "good news": they still had some talks open for 'very reasonable rates'. Huh??? Ken got the scoop from them. They wanted $2500 from us for a 20 minute talk. Whoever paid them $10k got to give the keynote address. Woopie! What a waste of time that whole thing was to even consider. I wonder if many of those attendees realized they were listening to speakers who BOUGHT their way in.



    Added: I emailed Ken the link the Kerry S' post.
  • Heater.Heater. Posts: 21,230
    edited 2014-04-09 06:03
    T Chap,
    Numbers are boring and don't "emote"
    Really:

    7, 007, 42, 69, 666, 1729,

    Those numbers don't move you?

    Back in the day we had the Motorola 6800, their 32 bit chip became the 68000.

    Zilog had the Z80 and their 32 bit chip became the Z8000.

    Something about all those zeros.
  • cgraceycgracey Posts: 14,133
    edited 2014-04-09 06:05
    ozpropdev wrote: »
    Chip

    Had a quick look
    COGRUN,COGINIT?
    Maybe a TASKID instruction

    Looks good! :)
    Brian

    Edit: PASSCNT?


    Oh, I was worried for a second, there. I was wondering how I could forget COGRUN, COGNEW, etc. The answer is, they all fall under the SYSOP umbrella. That will be used for the math circuits, too. Thanks for noticing, though.
  • T ChapT Chap Posts: 4,208
    edited 2014-04-09 06:08
    Hundreds of millions are spent on BMW's to establish their position in the marketplace. BMW is ubiquitous, non drivers know the difference. Highly paid research teams market the "3 series" to stimulate your emotions. The name is a number, and there are exceptions. Apple has spent tons also to market their software revisions" The only number that is used is generic "X". The flavor of the new revision is never about the number, it always includes a new graphic, new features but recent history always includes an animal association. Companies in marketing spend billions on research in trials, side by side tests, group studies. So, "people love to compare" for very good reason. It is not arbitrary or wasteful.
  • Heater.Heater. Posts: 21,230
    edited 2014-04-09 06:09
    Chip,

    Oh yeah, the conference circuit can be like that.

    But I'm sure that's not the case with distributors. They want to sell stuff as much as you do, there is no gain for them in making things hard to find. I imagine they don't know what a Propeller is either and it just gets lost somewhere "on the shelf at the back".
  • T ChapT Chap Posts: 4,208
    edited 2014-04-09 06:11
    Heater, the number alone does nothing much, the marketing behind 007 over decades does lot. Thousands of years of 666 references does a lot. It is NOT the number behind those references you make, but the history of associations.
  • cgraceycgracey Posts: 14,133
    edited 2014-04-09 06:12
    Heater. wrote: »
    Chip,

    Oh yeah, the conference circuit can be like that.

    But I'm sure that's not the case with distributors. They want to sell stuff as much as you do, there is no gain for them in making things hard to find. I imagine they don't know what a Propeller is either and it just gets lost somewhere "on the shelf at the back".


    I think they have some grounded interests in selling our products, but as it gets into their system, it gets lost for the reasons cited.
  • ozpropdevozpropdev Posts: 2,791
    edited 2014-04-09 06:18
    cgracey wrote: »
    Oh, I was worried for a second, there. I was wondering how I could forget COGRUN, COGNEW, etc. The answer is, they all fall under the SYSOP umbrella. That will be used for the math circuits, too. Thanks for noticing, though.
    No worries Chip.
    And what about PASSCNT?

    Edit: and SETZC?
  • Bill HenningBill Henning Posts: 6,445
    edited 2014-04-09 06:22
    Edit: Obsolete, Chip already said he would keep them - and give us 32!!! Sorry, I was replying to posts in order from the last time I read the thread.

    Chip,

    Locks are absolutely necessary in some form to allow multiple tasks / threads to access shared resources safely.

    Example: I allow multiple cogs to access the shared external memory on Morpheus, something I could not safely do without locks.

    If locks are removed, many things will become impossible (or dangerous).
    cgracey wrote: »
    Wow! Look at how few times LOCKSET and LOCKCLR were used: 3 and 7, only! I wonder if they were even needed, or used just because their existence suggested they were needed.

    I've never used these, myself, though I put them in the design because I could imagine they might be necessary, as some others now adamantly suppose. They've hardly been used on the OBEX, though. I would like to just get rid of them. There are other ways to do such things and, ideally, you wouldn't be writing code that required them. I think they might just be faking people out into thinking they are useful. In practice, I've never found them even remotely necessary. I SAY JETISSON THOSE THINGS! Anyone care, who's actually used them? Please speak up!
  • Bill HenningBill Henning Posts: 6,445
    edited 2014-04-09 06:23
    Whew! good.

    32 sounds great, if it does not take too much logic.
    cgracey wrote: »
    All right I'll keep them. How many would you ideally like to see in the design?
  • Kerry SKerry S Posts: 163
    edited 2014-04-09 06:24
    cgracey wrote: »
    There was some multi-core processing conference that we were polled to speat at, recently. They asked for submissions on ideas for talks, so we put something together and sent it to them, figuring it wouldn't hurt to speak about the Propeller at some conference. Well, they got back to us and said that the thing was filling up very quickly with 700 registered attendees and speaking spots were filling up fast, too, but there was some "good news": they still had some talks open for 'very reasonable rates'. Huh??? Ken got the scoop from them. They wanted $2500 from us for a 20 minute talk. Whoever paid them $10k got to give the keynote address. Woopie! What a waste of time that whole thing was to even consider. I wonder if many of those attendees realized they were listening to speakers who BOUGHT their way in.

    Pay to play is lame BUT sometimes you have to look at it as part of the marketing budget IF you can leverage it.

    For example if that conference was one that was well known then: Were they doing live streaming? Were they posting the speakers on-line (video)? Would they let you film the talk and post on your web site? IF they had a name people searched for and IF they would either post the video or let you post THEN that $2500.00 might have been a good investment. You could have put pages up on Parallax.com linking to it (with key words in the page to hit the search engines) and perhaps got others with Prop related sites to do the same (to raise your ranking). NOW your talk has the potential to reach a lot of people (via keyword search) AND you start to get your name out there with people who might not otherwise have heard of, or really thought about, Parallax and the Propeller as an option. You HAVE to have an almost evangelical visionary message that really grips people. Needs to tie in to what they do while gently opening their eyes to new concepts and possibilities. I have no doubt that the Propeller could be the source of such a speech/white paper! I see guys, and gals, walking out with the eyes wide going 'wow! I never thought about THAT before!'

    I had the pleasure of working with a small automation manufacturer in the way back. They were a no name UNTIL their president started hitting all of the trade conferences, started writing compelling articles for the trade magazines, and created a name for both the company and himself in the industry. That was all before the internet and <GOOGLE>!
  • Ken GraceyKen Gracey Posts: 7,386
    edited 2014-04-09 06:25
    cgracey wrote: »
    Ken needs to see this.

    Oh yeah, I'm already aware of this and I've tried to change it. There are two reasons for not being categorized correctly, and only one of them relates to our terminology being a bit unique. In these big corporations - and they're mostly the same - buyers handle similar product lines. Prior to making our first Propeller, we were a supplier of embedded tools - for the SX, the BASIC Stamp, and even the PIC. This is a product category in a distributor's view, assigned to a buyer who handles the product category. Once you're an embedded tools provider, and you introduce your first processor to 70 distributors, a bunch of them are going to trip up the listing no matter how much you manage them. While we now need to be represented by the internal semiconductor buyer, we've always been handled by "Joe, who does the Parallax stuff - the embedded tools". This is partly why ELFA has this goofy listing.

    From a distance it's situations like this that make engineers think marketing people are just plain stupid.

    And I've tried to fix this problem with ELFA. I've concluded that it's not in your benefit to have me spend my time on that particular case. I can only afford to give it another inquiry by Skype to our buyer. I'll do that, but I'm not putting 20 hours into resolving this problem or flying to Sweden anytime soon.

    To address the distribution and listing issue, Parallax's strategy moving forward with P2 is to focus on three distributors exclusively (Mouser, Digi-Key and RS Components). All of these distributors have capable buyers and we have available bandwidth to communicate effectively with them. While you'll be able to buy all of our products at any distributor, it's these three who will be responsible for the introduction and communication of our new product to the market place, with us. They come to our office regularly and they understand what's going on with our product plan, even though it's changing. They lurk here, too, but they don't post anything.

    - - - -

    Regarding terminology - and I see other threads have been started for it - sometimes being "unique" also means being "alone". Not only have we been standing in the corner of the playground while others played games together, we were also speaking our own language. Why make it difficult on ourselves? This is why I advocate we strongly use the word "core" and "shared RAM" and that we come to the playground speaking both our own language Spin and what everybody else wants to speak: C. I can prove the effectiveness of being bilingual with the recent Propeller C program. For the first time, educators are interested in looking at Spin because we support C! Prior to having C support they really didnt want to know about Spin. It we release Spin only again, we'll deserve every benefit of being unique.

    Ken Gracey
  • Heater.Heater. Posts: 21,230
    edited 2014-04-09 06:27
    T Chap,
    It is NOT the number behind those references you make, but the history of associations
    Yes exactly. Same with any actual words you might use. or even words you might make up.

    Motorola could have called their chip the 79360 or whatever random looking number but no it had to be 68000.
  • Heater.Heater. Posts: 21,230
    edited 2014-04-09 06:32
    Ken,

    OK well said. Yes I can imagine ELFA is a bit out of the way for you.
  • Bill HenningBill Henning Posts: 6,445
    edited 2014-04-09 06:39
    16 cogs, with the potential of four tasks each?

    Sounds like a winner to me.

    One feature of the tasks we have on the P2 that I REALLY liked was the advanced debugging it made possible.
    cgracey wrote: »
    Two tasks are good, but four are really plush. Actually, I've found that three tasks are usually optimal. Four is overkill, but two are too few. Three is just odd, so might as well go with four. In my usage, there is always a main task and a few helper tasks which run in loops and don't do any calls. They are like adding magic peripherals that never could have been anticipated in the chip hardware design. That's what I think of extra tasks: they are peripherals.

    Multitasking is very simple. It's just a matter of mux'ing a few sets of Z/C/PC. That's all it needs to be.
  • Ken GraceyKen Gracey Posts: 7,386
    edited 2014-04-09 06:43
    Heater. wrote: »
    Ken,

    OK well said. Yes I can imagine ELFA is a bit out of the way for you.

    I'll set out to fix that Mouser and Digi-Key wonky listing today. That'll be easy to do by comparison to the ELFA problem, but I'll give it another shot.

    Ken Gracey
  • RamonRamon Posts: 484
    edited 2014-04-09 06:47
    cgracey wrote: »
    I think you are right, and I read your post about ELFA. I've noticed the same thing when I've bothered to search on Digi-Key or Mouser. It always makes me wince when I see stuff like that. But, you know, I always imagined there wasn't much we could do about it, because Parallax doesn't "pay to play" all the industry marketing games, and we are not favored by the system, so to speak.

    Quite true. I appreciate that you talk about this with complete freedom, as nobody inside the industry talks clearly about these "practices".

    Everyone can easily check it: write "xilinx" at mouser's site. OMG, it turns out to be Al.... !

    I usually check parts on several distributors. Its quite interesting to see that each distributor has its "friends".

    (PS: Another day we can also talk about EDA tools and semiconductor industry, or maybe not. No, Its better not to talk about this if we want propeller to be done at smaller geometry than 180nm. I hope sharks not to be "smelling" around here)
  • Alex.StanfieldAlex.Stanfield Posts: 198
    edited 2014-04-09 06:50
    W9GFO wrote: »
    It ends with the smart IO pins! Or maybe they should be called "IIO" Pins (Intelligent IO).

    Better yet, IO - Intelligent, or "IOI". [noparse] :D[/noparse]

    How about "i-Pin" (Intelligent Pin) ??

    Alex
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