A simpler COG
Ale
Posts: 2,363
Having loads of time to think, and less time to sit down at the keyboard, brought me the possibility of doing some fpga work. While the ultimate goal may be the 1048576-bit parallel processor implemented in the Tornado5000 series to be developed on the next century, I have meanwhile decided that the constrains imposed by a Lattice MachXO2-1200 allows for interesting possibilities.
One of them is a COG. Yes, our beloved Propeller series I cog. (I know that some have done this already but I haven't seen any code yet).
With time to think, and pencil and paper I have been exploring with multiple archtectures. And finaly settled, for the time being, for a COG. But mine is a bit different. So, no code compability. But important are the concepts that lead to its simplicity: The sequencer has its work cut in half because all these bits for flags and result handling, dual ported memory for reading s and d cocurrently avoid extra muxes.
I also increased the. memory to 1024 locations. Some conditions had to go too to make room for the extra space, those conditions are not used that often, then I thought extra space is better
. The FPGA is some 85 % full.
One of them is a COG. Yes, our beloved Propeller series I cog. (I know that some have done this already but I haven't seen any code yet).
With time to think, and pencil and paper I have been exploring with multiple archtectures. And finaly settled, for the time being, for a COG. But mine is a bit different. So, no code compability. But important are the concepts that lead to its simplicity: The sequencer has its work cut in half because all these bits for flags and result handling, dual ported memory for reading s and d cocurrently avoid extra muxes.
I also increased the. memory to 1024 locations. Some conditions had to go too to make room for the extra space, those conditions are not used that often, then I thought extra space is better
. The FPGA is some 85 % full.
Comments
That makes it a whole lot more flexible and matters even more on a single COG design.
What speed does your COG run at ?
Here some simulation waveforms.
Regarding the frequency, the compiler said something about 10 Mhz, that is in the slowest of the MachXO2 series, with an 8x8 multiplier
Chip gave some details in the Prop 2 threads. IIRC he managed a late-change to add threading, without a clock penalty.
To time-slice, you create multiple Opcode Fetch Pointers (ProgramCounters) and Flags, and then flip those to the CPU engine, on a time-sliced manner.
You need to decide how many PC.FLAG copies (or threads) are to be supported, and give some way to weight them.
Simple Equal time, is less flexible than something like a 4 way copy, which needs 2 bits to map, and one can fit 16 x 1:4 allocate slots into a 32 bit register.
You might choose to allocate every second one to the most critical Thread, giving that 50% CPU thruput (still jitter free, but at half the clock speed), and the remaining 8 slots could map as 3/16:3/16:2/16, or 4/16, 3/16 and 1/16, or 7/16, 1/16, 0/16 etc.
Or, you may decide to allow some modulus bits, to cover cases 1/3 1/3 1/3 mapping.
But I am thinkering a bit more with an external memory interface. RDBYTE/WRBYTE should access external memory directly... let's see with what I can come up.
Thanks!
I wonder how difficult it would be to port your design to a Cyclone IV? I guess that partly depends on whether you used an HDL or building blocks from a Lattice library. Anyway, if your COG is sufficiently lean, perhaps several would fit on on a DE0-Nano. More cogs plus higher speed would make a most interesting design to play with!
Or how about an engine that executes Spin bytecodes directly?
Yes, you have an interesting project indeed.
Flexible time slices and mapping multiple thread execution register sets (PC, C, Z, etc.) as well as bank switching would be very fine enhancements to the current architecture. But more important, at least in my opinion, would be the provision for indirect addressing. The current cog can already quite effectively do task switching, but is crippled somewhat by the lack if indirect operations.
Solving this latter issue would really make a cog shine !
Cheers,
Peter (pjv)
It went through my mind something like a spin bytecode interpreter, that would be cool, maybe microcoded
Indirect addressing would need and extra field in the opcode map... And there is no space for it, Maybe autoincrement/decrement... Maybe another encoding for the flags/effects should ge impemented... 7 bits are quite a... bit!
Microcoded instruction sets for various languages(Pascal, Modula-2, Prolog, LISP, Java) have been done but there isn't much of a performance gain. Once the Intel 32bit microprocessors started taking off, it killed the market for these microcoded beasts.
But if one wants to study how to implement it, take a look at the Symbolics workstations. It's fascinating stuff.
Since this is custom, and you are doing external memory, I would suggest to include SPI RAM and SPI FLASH HW options. (QSPI where possible, with options for Dual chips, to do 8 wide SPI )
Really fast stuff is managed on-chip, but once you go to LMM byte-code style, the speed impact of going serial can be greatly reduced with proper HW support.
The only reason this works is because the P2 has a 4 stage pipeline. If he copies the P1, there isn't any chance of it having this feature, because the 4 stage pipeline imposes so many restrictions on code execution that the P1 doesn't.
They're as different as apples and oranges.
I'm not following the logic here. This has been done in P2, in spite of the 4 stage pipeline imposes so many restrictions on code execution
- which has to make it easier to do, in a CPLD version, than in P2, rather than harder ?
The Op has already said in #5 that he thinks a 2:1 Slicer is (relatively) easy to do..
The P2 and P1 *are* similar in that the P1 does the 4 stages of execution in 4 consecutive clocks, while the P2 interleaves 4 instructions across 4 stages and 4 clocks. When you combine this with the multi-threading, it actually takes 16 clocks for 4 instructions to enter and exit the pipeline, because although the P2 executes 4 instructions in 4 clocks, the pipeline is 4 stages deep and the currently finishing instruction was loaded 4 clocks ago.
I think if you used a DE0-Nano it might gain some traction as those of us that already have one might find the time to assist.
If you (and others) come up with something interesting, once the P2 is out in production, Chip/Parallax might be interested in adding it into a P1 or P2 variant.
i have also a board with a spartan2-100, and one with a spartan3-200, the DE0-nano will be the birthday's gift that I'll ger as long as I order it
I am writing down some documentation and diagrams, I want to see if I can speed it up a bit, it is rather slow. With the combinatorial multiplier it should do some 6.5 MHz.
Multiply is a rare opcode, and often systems pipeline it, which saves a lot of logic, and you may be able to make it larger./ Size variable.
Adding an opcode like WAITMATH would work like WAITxx, allowing you to pack in other instructions that did not use the result, and wait for the result if you need to, with minimal looping cost.
Note another opcode in Prop 2 is the REPEAT - that does a 'zero overhead loop', where you specify a loop count, and block size,
and a parallel hardware circuit does DJNZ
Prop 2 also allowed a timeout on some Waits...
On the spartan2 it can do 18 MHz.
I have been thinking about the threading vs pipeline and a 2 way threading can be done sort of easily, interlocking the fetch, registers load and writeback. At least on paper is possible, I'll have to check to see how slow it becomes due to the extra address muxes and related logic.
I have to write some docs and publish them, with diagrams!, those I have to do too
The picture shows a bit the simulation of the sequencer and the memory. The two threads are labeled t1&t2. The marker shows where the first thread starts execution. One clock before memory is read to get the opcode. The slots or states are Fetch S&D T1, Fetch Opcode & WB T2, Fetch S&D T2 and Fetch Opcode & WB T1. I have to add the ALU and see if it fits the MachXO2. A Spartan2-100 would probably be 50% full.
The file tb_v8.v can be compiled with icarus verilog.
$ iverilog tb_v8.v
and run with vvp
$ vvp a.out
that will create a waveform file, dump.vcd (also provided) that can be displayed with GTKWave.
What it does...
Thread one starts at address 0 and executes a call to $004 with ret at $022. Thread 2 starts after one instruction of t1 at address $20, at address $22 it finds the written jmp of thread 1. For the time being only the memory and the sequencer are included. Feel free to try it out !.
That can pipeline, so should have no speed-cost. Default could be 1:1 for 50% CPU.
It would nudge the HW a little, ( a tiny %) but I could see that Two wide-ish load values could be quite useful ?
That would allow Video threading for example. 0 is off, and 1..N is that many cycles on that thread.
examples would be
A:B 1:1 run high speed 50%/50%
A:B 0:1 B has 100%, A is off
A:B 1:0 A has 100%, B is off
A:B 480:110 A has 100% for 480 clocks, then B has 110 clocks
A:B 9:1 A has 90%, B has 10%
Either thread could change A:B, and it would apply on the next load.
here is the report for the attached version.
It has two threads, but I havent tested it, only the one thread version. It should run at 24 MHz, witht booth signed multiplier and all
Place & Route TRACE Report Loading design for application trce from file pnutdsp_lattice_pnutdsp_lattice.ncd. Design name: pnutdsp_top NCD version: 3.2 Vendor: LATTICE Device: LCMXO2-1200ZE Package: TQFP144 Performance: 1 Loading device for application trce from file 'xo2c1200.nph' in environment: C:/lscc/diamond/1.4/ispfpga. Package Status: Final Version 1.33 Performance Hardware Data Status: Final Version 22.4 Setup and Hold Report -------------------------------------------------------------------------------- Lattice TRACE Report - Setup, Version Diamond_1.4_Production (87) Sun Apr 07 08:52:00 2013 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2011 Lattice Semiconductor Corporation, All rights reserved. Report Information ------------------ Command line: trce -v 10 -gt -sethld -sp 1 -sphld m -o pnutdsp_lattice_pnutdsp_lattice.twr pnutdsp_lattice_pnutdsp_lattice.ncd pnutdsp_lattice_pnutdsp_lattice.prf Design file: pnutdsp_lattice_pnutdsp_lattice.ncd Preference file: pnutdsp_lattice_pnutdsp_lattice.prf Device,speed: LCMXO2-1200ZE,1 Report level: verbose report, limited to 10 items per preference -------------------------------------------------------------------------------- Preference Summary FREQUENCY NET "CLK_I_inferred_clock" 20.460000 MHz (0 errors) 4096 items scored, 0 timing errors detected. Report: 24.534MHz is the maximum frequency for this preference. BLOCK ASYNCPATHS BLOCK RESETPATHS -------------------------------------------------------------------------------- ================================================================================ Preference: FREQUENCY NET "CLK_I_inferred_clock" 20.460000 MHz ; 4096 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- Passed: The following path meets requirements by 8.116ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q II_1/alu/d_out_1 (from II_1/alu/un1_d_out126_0 +) Destination: FF Data in II_1/imem/ptr1_t1_r_9 (to CLK_I_inferred_clock +) Delay: 19.153ns (31.7% logic, 68.3% route), 7 logic levels. Constraint Details: 19.153ns physical path delay II_1/alu/SLICE_189 to II_1/imem/SLICE_152 meets 48.875ns delay constraint less 21.174ns skew and 0.432ns DIN_SET requirement (totaling 27.269ns) by 8.116ns Physical Path Details: Data path II_1/alu/SLICE_189 to II_1/imem/SLICE_152: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.955 R5C9A.CLK to R5C9A.Q1 II_1/alu/SLICE_189 (from II_1/alu/un1_d_out126_0) ROUTE 1 6.800 R5C9A.Q1 to R5C14A.A1 II_1/alu_out_1 CTOF_DEL --- 0.923 R5C14A.A1 to R5C14A.F1 II_1/SLICE_275 ROUTE 6 6.279 R5C14A.F1 to R2C14B.B0 DIN_O_c_1 C0TOFCO_DE --- 2.064 R2C14B.B0 to R2C14B.FCO II_1/imem/SLICE_156 ROUTE 1 0.000 R2C14B.FCO to R2C14C.FCI II_1/imem/ptr1_t1_r_cry_2 FCITOFCO_D --- 0.317 R2C14C.FCI to R2C14C.FCO II_1/imem/SLICE_155 ROUTE 1 0.000 R2C14C.FCO to R2C14D.FCI II_1/imem/ptr1_t1_r_cry_4 FCITOFCO_D --- 0.317 R2C14D.FCI to R2C14D.FCO II_1/imem/SLICE_154 ROUTE 1 0.000 R2C14D.FCO to R2C15A.FCI II_1/imem/ptr1_t1_r_cry_6 FCITOFCO_D --- 0.317 R2C15A.FCI to R2C15A.FCO II_1/imem/SLICE_153 ROUTE 1 0.000 R2C15A.FCO to R2C15B.FCI II_1/imem/ptr1_t1_r_cry_8 FCITOF0_DE --- 1.181 R2C15B.FCI to R2C15B.F0 II_1/imem/SLICE_152 ROUTE 1 0.000 R2C15B.F0 to R2C15B.DI0 II_1/imem/ptr1_t1_r_s_9 (to CLK_I_inferred_clock) -------- 19.153 (31.7% logic, 68.3% route), 7 logic levels. Clock Skew Details: Source Clock Path iosc to II_1/alu/SLICE_189: Name Fanout Delay (ns) Site Resource ROUTE 144 7.878 OSC.OSC to R9C13C.CLK CLK_I_inferred_clock REG_DEL --- 0.955 R9C13C.CLK to R9C13C.Q0 SLICE_294 ROUTE 33 5.856 R9C13C.Q0 to R5C11A.A1 II_1/opcode_t1_29 CTOF_DEL --- 0.923 R5C11A.A1 to R5C11A.F1 II_1/alu/SLICE_436 ROUTE 2 3.386 R5C11A.F1 to R2C13D.B0 II_1/alu/un1_d_out126_0_a2_0_0 CTOOFX_DEL --- 1.359 R2C13D.B0 to R2C13D.OFX0 II_1/alu/un1_d_out126_0/SLICE_297 ROUTE 17 8.695 R2C13D.OFX0 to R5C9A.CLK II_1/alu/un1_d_out126_0 -------- 29.052 (11.1% logic, 88.9% route), 3 logic levels. Destination Clock Path iosc to II_1/imem/SLICE_152: Name Fanout Delay (ns) Site Resource ROUTE 144 7.878 OSC.OSC to R2C15B.CLK CLK_I_inferred_clock -------- 7.878 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 8.157ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q II_1/alu/d_out_1 (from II_1/alu/un1_d_out126_0 +) Destination: FF Data in II_1/imem/ptr0_t1_r_9 (to CLK_I_inferred_clock +) Delay: 19.112ns (31.8% logic, 68.2% route), 7 logic levels. Constraint Details: 19.112ns physical path delay II_1/alu/SLICE_189 to II_1/imem/SLICE_158 meets 48.875ns delay constraint less 21.174ns skew and 0.432ns DIN_SET requirement (totaling 27.269ns) by 8.157ns Physical Path Details: Data path II_1/alu/SLICE_189 to II_1/imem/SLICE_158: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.955 R5C9A.CLK to R5C9A.Q1 II_1/alu/SLICE_189 (from II_1/alu/un1_d_out126_0) ROUTE 1 6.800 R5C9A.Q1 to R5C14A.A1 II_1/alu_out_1 CTOF_DEL --- 0.923 R5C14A.A1 to R5C14A.F1 II_1/SLICE_275 ROUTE 6 6.238 R5C14A.F1 to R2C16B.A0 DIN_O_c_1 C0TOFCO_DE --- 2.064 R2C16B.A0 to R2C16B.FCO II_1/imem/SLICE_162 ROUTE 1 0.000 R2C16B.FCO to R2C16C.FCI II_1/imem/ptr0_t1_r_cry_2 FCITOFCO_D --- 0.317 R2C16C.FCI to R2C16C.FCO II_1/imem/SLICE_161 ROUTE 1 0.000 R2C16C.FCO to R2C16D.FCI II_1/imem/ptr0_t1_r_cry_4 FCITOFCO_D --- 0.317 R2C16D.FCI to R2C16D.FCO II_1/imem/SLICE_160 ROUTE 1 0.000 R2C16D.FCO to R2C17A.FCI II_1/imem/ptr0_t1_r_cry_6 FCITOFCO_D --- 0.317 R2C17A.FCI to R2C17A.FCO II_1/imem/SLICE_159 ROUTE 1 0.000 R2C17A.FCO to R2C17B.FCI II_1/imem/ptr0_t1_r_cry_8 FCITOF0_DE --- 1.181 R2C17B.FCI to R2C17B.F0 II_1/imem/SLICE_158 ROUTE 1 0.000 R2C17B.F0 to R2C17B.DI0 II_1/imem/ptr0_t1_r_s_9 (to CLK_I_inferred_clock) -------- 19.112 (31.8% logic, 68.2% route), 7 logic levels. Clock Skew Details: Source Clock Path iosc to II_1/alu/SLICE_189: Name Fanout Delay (ns) Site Resource ROUTE 144 7.878 OSC.OSC to R9C13C.CLK CLK_I_inferred_clock REG_DEL --- 0.955 R9C13C.CLK to R9C13C.Q0 SLICE_294 ROUTE 33 5.856 R9C13C.Q0 to R5C11A.A1 II_1/opcode_t1_29 CTOF_DEL --- 0.923 R5C11A.A1 to R5C11A.F1 II_1/alu/SLICE_436 ROUTE 2 3.386 R5C11A.F1 to R2C13D.B0 II_1/alu/un1_d_out126_0_a2_0_0 CTOOFX_DEL --- 1.359 R2C13D.B0 to R2C13D.OFX0 II_1/alu/un1_d_out126_0/SLICE_297 ROUTE 17 8.695 R2C13D.OFX0 to R5C9A.CLK II_1/alu/un1_d_out126_0 -------- 29.052 (11.1% logic, 88.9% route), 3 logic levels. Destination Clock Path iosc to II_1/imem/SLICE_158: Name Fanout Delay (ns) Site Resource ROUTE 144 7.878 OSC.OSC to R2C17B.CLK CLK_I_inferred_clock -------- 7.878 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 8.316ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q II_1/alu/d_out_1 (from II_1/alu/un1_d_out126_0 +) Destination: FF Data in II_1/imem/ptr1_t1_r_8 (to CLK_I_inferred_clock +) Delay: 18.953ns (31.0% logic, 69.0% route), 6 logic levels. Constraint Details: 18.953ns physical path delay II_1/alu/SLICE_189 to II_1/imem/SLICE_153 meets 48.875ns delay constraint less 21.174ns skew and 0.432ns DIN_SET requirement (totaling 27.269ns) by 8.316ns Physical Path Details: Data path II_1/alu/SLICE_189 to II_1/imem/SLICE_153: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.955 R5C9A.CLK to R5C9A.Q1 II_1/alu/SLICE_189 (from II_1/alu/un1_d_out126_0) ROUTE 1 6.800 R5C9A.Q1 to R5C14A.A1 II_1/alu_out_1 CTOF_DEL --- 0.923 R5C14A.A1 to R5C14A.F1 II_1/SLICE_275 ROUTE 6 6.279 R5C14A.F1 to R2C14B.B0 DIN_O_c_1 C0TOFCO_DE --- 2.064 R2C14B.B0 to R2C14B.FCO II_1/imem/SLICE_156 ROUTE 1 0.000 R2C14B.FCO to R2C14C.FCI II_1/imem/ptr1_t1_r_cry_2 FCITOFCO_D --- 0.317 R2C14C.FCI to R2C14C.FCO II_1/imem/SLICE_155 ROUTE 1 0.000 R2C14C.FCO to R2C14D.FCI II_1/imem/ptr1_t1_r_cry_4 FCITOFCO_D --- 0.317 R2C14D.FCI to R2C14D.FCO II_1/imem/SLICE_154 ROUTE 1 0.000 R2C14D.FCO to R2C15A.FCI II_1/imem/ptr1_t1_r_cry_6 FCITOF1_DE --- 1.298 R2C15A.FCI to R2C15A.F1 II_1/imem/SLICE_153 ROUTE 1 0.000 R2C15A.F1 to R2C15A.DI1 II_1/imem/ptr1_t1_r_s_8 (to CLK_I_inferred_clock) -------- 18.953 (31.0% logic, 69.0% route), 6 logic levels. Clock Skew Details: Source Clock Path iosc to II_1/alu/SLICE_189: Name Fanout Delay (ns) Site Resource ROUTE 144 7.878 OSC.OSC to R9C13C.CLK CLK_I_inferred_clock REG_DEL --- 0.955 R9C13C.CLK to R9C13C.Q0 SLICE_294 ROUTE 33 5.856 R9C13C.Q0 to R5C11A.A1 II_1/opcode_t1_29 CTOF_DEL --- 0.923 R5C11A.A1 to R5C11A.F1 II_1/alu/SLICE_436 ROUTE 2 3.386 R5C11A.F1 to R2C13D.B0 II_1/alu/un1_d_out126_0_a2_0_0 CTOOFX_DEL --- 1.359 R2C13D.B0 to R2C13D.OFX0 II_1/alu/un1_d_out126_0/SLICE_297 ROUTE 17 8.695 R2C13D.OFX0 to R5C9A.CLK II_1/alu/un1_d_out126_0 -------- 29.052 (11.1% logic, 88.9% route), 3 logic levels. Destination Clock Path iosc to II_1/imem/SLICE_153: Name Fanout Delay (ns) Site Resource ROUTE 144 7.878 OSC.OSC to R2C15A.CLK CLK_I_inferred_clock -------- 7.878 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 8.357ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q II_1/alu/d_out_1 (from II_1/alu/un1_d_out126_0 +) Destination: FF Data in II_1/imem/ptr0_t1_r_8 (to CLK_I_inferred_clock +) Delay: 18.912ns (31.1% logic, 68.9% route), 6 logic levels. Constraint Details: 18.912ns physical path delay II_1/alu/SLICE_189 to II_1/imem/SLICE_159 meets 48.875ns delay constraint less 21.174ns skew and 0.432ns DIN_SET requirement (totaling 27.269ns) by 8.357ns Physical Path Details: Data path II_1/alu/SLICE_189 to II_1/imem/SLICE_159: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.955 R5C9A.CLK to R5C9A.Q1 II_1/alu/SLICE_189 (from II_1/alu/un1_d_out126_0) ROUTE 1 6.800 R5C9A.Q1 to R5C14A.A1 II_1/alu_out_1 CTOF_DEL --- 0.923 R5C14A.A1 to R5C14A.F1 II_1/SLICE_275 ROUTE 6 6.238 R5C14A.F1 to R2C16B.A0 DIN_O_c_1 C0TOFCO_DE --- 2.064 R2C16B.A0 to R2C16B.FCO II_1/imem/SLICE_162 ROUTE 1 0.000 R2C16B.FCO to R2C16C.FCI II_1/imem/ptr0_t1_r_cry_2 FCITOFCO_D --- 0.317 R2C16C.FCI to R2C16C.FCO II_1/imem/SLICE_161 ROUTE 1 0.000 R2C16C.FCO to R2C16D.FCI II_1/imem/ptr0_t1_r_cry_4 FCITOFCO_D --- 0.317 R2C16D.FCI to R2C16D.FCO II_1/imem/SLICE_160 ROUTE 1 0.000 R2C16D.FCO to R2C17A.FCI II_1/imem/ptr0_t1_r_cry_6 FCITOF1_DE --- 1.298 R2C17A.FCI to R2C17A.F1 II_1/imem/SLICE_159 ROUTE 1 0.000 R2C17A.F1 to R2C17A.DI1 II_1/imem/ptr0_t1_r_s_8 (to CLK_I_inferred_clock) -------- 18.912 (31.1% logic, 68.9% route), 6 logic levels. Clock Skew Details: Source Clock Path iosc to II_1/alu/SLICE_189: Name Fanout Delay (ns) Site Resource ROUTE 144 7.878 OSC.OSC to R9C13C.CLK CLK_I_inferred_clock REG_DEL --- 0.955 R9C13C.CLK to R9C13C.Q0 SLICE_294 ROUTE 33 5.856 R9C13C.Q0 to R5C11A.A1 II_1/opcode_t1_29 CTOF_DEL --- 0.923 R5C11A.A1 to R5C11A.F1 II_1/alu/SLICE_436 ROUTE 2 3.386 R5C11A.F1 to R2C13D.B0 II_1/alu/un1_d_out126_0_a2_0_0 CTOOFX_DEL --- 1.359 R2C13D.B0 to R2C13D.OFX0 II_1/alu/un1_d_out126_0/SLICE_297 ROUTE 17 8.695 R2C13D.OFX0 to R5C9A.CLK II_1/alu/un1_d_out126_0 -------- 29.052 (11.1% logic, 88.9% route), 3 logic levels. Destination Clock Path iosc to II_1/imem/SLICE_159: Name Fanout Delay (ns) Site Resource ROUTE 144 7.878 OSC.OSC to R2C17A.CLK CLK_I_inferred_clock -------- 7.878 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 8.433ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q II_1/alu/d_out_1 (from II_1/alu/un1_d_out126_0 +) Destination: FF Data in II_1/imem/ptr1_t1_r_7 (to CLK_I_inferred_clock +) Delay: 18.836ns (30.6% logic, 69.4% route), 6 logic levels. Constraint Details: 18.836ns physical path delay II_1/alu/SLICE_189 to II_1/imem/SLICE_153 meets 48.875ns delay constraint less 21.174ns skew and 0.432ns DIN_SET requirement (totaling 27.269ns) by 8.433ns Physical Path Details: Data path II_1/alu/SLICE_189 to II_1/imem/SLICE_153: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.955 R5C9A.CLK to R5C9A.Q1 II_1/alu/SLICE_189 (from II_1/alu/un1_d_out126_0) ROUTE 1 6.800 R5C9A.Q1 to R5C14A.A1 II_1/alu_out_1 CTOF_DEL --- 0.923 R5C14A.A1 to R5C14A.F1 II_1/SLICE_275 ROUTE 6 6.279 R5C14A.F1 to R2C14B.B0 DIN_O_c_1 C0TOFCO_DE --- 2.064 R2C14B.B0 to R2C14B.FCO II_1/imem/SLICE_156 ROUTE 1 0.000 R2C14B.FCO to R2C14C.FCI II_1/imem/ptr1_t1_r_cry_2 FCITOFCO_D --- 0.317 R2C14C.FCI to R2C14C.FCO II_1/imem/SLICE_155 ROUTE 1 0.000 R2C14C.FCO to R2C14D.FCI II_1/imem/ptr1_t1_r_cry_4 FCITOFCO_D --- 0.317 R2C14D.FCI to R2C14D.FCO II_1/imem/SLICE_154 ROUTE 1 0.000 R2C14D.FCO to R2C15A.FCI II_1/imem/ptr1_t1_r_cry_6 FCITOF0_DE --- 1.181 R2C15A.FCI to R2C15A.F0 II_1/imem/SLICE_153 ROUTE 1 0.000 R2C15A.F0 to R2C15A.DI0 II_1/imem/ptr1_t1_r_s_7 (to CLK_I_inferred_clock) -------- 18.836 (30.6% logic, 69.4% route), 6 logic levels. Clock Skew Details: Source Clock Path iosc to II_1/alu/SLICE_189: Name Fanout Delay (ns) Site Resource ROUTE 144 7.878 OSC.OSC to R9C13C.CLK CLK_I_inferred_clock REG_DEL --- 0.955 R9C13C.CLK to R9C13C.Q0 SLICE_294 ROUTE 33 5.856 R9C13C.Q0 to R5C11A.A1 II_1/opcode_t1_29 CTOF_DEL --- 0.923 R5C11A.A1 to R5C11A.F1 II_1/alu/SLICE_436 ROUTE 2 3.386 R5C11A.F1 to R2C13D.B0 II_1/alu/un1_d_out126_0_a2_0_0 CTOOFX_DEL --- 1.359 R2C13D.B0 to R2C13D.OFX0 II_1/alu/un1_d_out126_0/SLICE_297 ROUTE 17 8.695 R2C13D.OFX0 to R5C9A.CLK II_1/alu/un1_d_out126_0 -------- 29.052 (11.1% logic, 88.9% route), 3 logic levels. Destination Clock Path iosc to II_1/imem/SLICE_153: Name Fanout Delay (ns) Site Resource ROUTE 144 7.878 OSC.OSC to R2C15A.CLK CLK_I_inferred_clock -------- 7.878 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 8.474ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q II_1/alu/d_out_1 (from II_1/alu/un1_d_out126_0 +) Destination: FF Data in II_1/imem/ptr0_t1_r_7 (to CLK_I_inferred_clock +) Delay: 18.795ns (30.6% logic, 69.4% route), 6 logic levels. Constraint Details: 18.795ns physical path delay II_1/alu/SLICE_189 to II_1/imem/SLICE_159 meets 48.875ns delay constraint less 21.174ns skew and 0.432ns DIN_SET requirement (totaling 27.269ns) by 8.474ns Physical Path Details: Data path II_1/alu/SLICE_189 to II_1/imem/SLICE_159: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.955 R5C9A.CLK to R5C9A.Q1 II_1/alu/SLICE_189 (from II_1/alu/un1_d_out126_0) ROUTE 1 6.800 R5C9A.Q1 to R5C14A.A1 II_1/alu_out_1 CTOF_DEL --- 0.923 R5C14A.A1 to R5C14A.F1 II_1/SLICE_275 ROUTE 6 6.238 R5C14A.F1 to R2C16B.A0 DIN_O_c_1 C0TOFCO_DE --- 2.064 R2C16B.A0 to R2C16B.FCO II_1/imem/SLICE_162 ROUTE 1 0.000 R2C16B.FCO to R2C16C.FCI II_1/imem/ptr0_t1_r_cry_2 FCITOFCO_D --- 0.317 R2C16C.FCI to R2C16C.FCO II_1/imem/SLICE_161 ROUTE 1 0.000 R2C16C.FCO to R2C16D.FCI II_1/imem/ptr0_t1_r_cry_4 FCITOFCO_D --- 0.317 R2C16D.FCI to R2C16D.FCO II_1/imem/SLICE_160 ROUTE 1 0.000 R2C16D.FCO to R2C17A.FCI II_1/imem/ptr0_t1_r_cry_6 FCITOF0_DE --- 1.181 R2C17A.FCI to R2C17A.F0 II_1/imem/SLICE_159 ROUTE 1 0.000 R2C17A.F0 to R2C17A.DI0 II_1/imem/ptr0_t1_r_s_7 (to CLK_I_inferred_clock) -------- 18.795 (30.6% logic, 69.4% route), 6 logic levels. Clock Skew Details: Source Clock Path iosc to II_1/alu/SLICE_189: Name Fanout Delay (ns) Site Resource ROUTE 144 7.878 OSC.OSC to R9C13C.CLK CLK_I_inferred_clock REG_DEL --- 0.955 R9C13C.CLK to R9C13C.Q0 SLICE_294 ROUTE 33 5.856 R9C13C.Q0 to R5C11A.A1 II_1/opcode_t1_29 CTOF_DEL --- 0.923 R5C11A.A1 to R5C11A.F1 II_1/alu/SLICE_436 ROUTE 2 3.386 R5C11A.F1 to R2C13D.B0 II_1/alu/un1_d_out126_0_a2_0_0 CTOOFX_DEL --- 1.359 R2C13D.B0 to R2C13D.OFX0 II_1/alu/un1_d_out126_0/SLICE_297 ROUTE 17 8.695 R2C13D.OFX0 to R5C9A.CLK II_1/alu/un1_d_out126_0 -------- 29.052 (11.1% logic, 88.9% route), 3 logic levels. Destination Clock Path iosc to II_1/imem/SLICE_159: Name Fanout Delay (ns) Site Resource ROUTE 144 7.878 OSC.OSC to R2C17A.CLK CLK_I_inferred_clock -------- 7.878 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 8.549ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q II_1/alu/d_out_2 (from II_1/alu/un1_d_out126_0 +) Destination: FF Data in II_1/imem/ptr0_t1_r_9 (to CLK_I_inferred_clock +) Delay: 18.720ns (31.0% logic, 69.0% route), 7 logic levels. Constraint Details: 18.720ns physical path delay II_1/alu/SLICE_190 to II_1/imem/SLICE_158 meets 48.875ns delay constraint less 21.174ns skew and 0.432ns DIN_SET requirement (totaling 27.269ns) by 8.549ns Physical Path Details: Data path II_1/alu/SLICE_190 to II_1/imem/SLICE_158: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.955 R5C10C.CLK to R5C10C.Q0 II_1/alu/SLICE_190 (from II_1/alu/un1_d_out126_0) ROUTE 1 6.969 R5C10C.Q0 to R5C15A.A0 II_1/alu_out_2 CTOF_DEL --- 0.923 R5C15A.A0 to R5C15A.F0 II_1/SLICE_276 ROUTE 6 5.946 R5C15A.F0 to R2C16B.A1 DIN_O_c_2 C1TOFCO_DE --- 1.795 R2C16B.A1 to R2C16B.FCO II_1/imem/SLICE_162 ROUTE 1 0.000 R2C16B.FCO to R2C16C.FCI II_1/imem/ptr0_t1_r_cry_2 FCITOFCO_D --- 0.317 R2C16C.FCI to R2C16C.FCO II_1/imem/SLICE_161 ROUTE 1 0.000 R2C16C.FCO to R2C16D.FCI II_1/imem/ptr0_t1_r_cry_4 FCITOFCO_D --- 0.317 R2C16D.FCI to R2C16D.FCO II_1/imem/SLICE_160 ROUTE 1 0.000 R2C16D.FCO to R2C17A.FCI II_1/imem/ptr0_t1_r_cry_6 FCITOFCO_D --- 0.317 R2C17A.FCI to R2C17A.FCO II_1/imem/SLICE_159 ROUTE 1 0.000 R2C17A.FCO to R2C17B.FCI II_1/imem/ptr0_t1_r_cry_8 FCITOF0_DE --- 1.181 R2C17B.FCI to R2C17B.F0 II_1/imem/SLICE_158 ROUTE 1 0.000 R2C17B.F0 to R2C17B.DI0 II_1/imem/ptr0_t1_r_s_9 (to CLK_I_inferred_clock) -------- 18.720 (31.0% logic, 69.0% route), 7 logic levels. Clock Skew Details: Source Clock Path iosc to II_1/alu/SLICE_190: Name Fanout Delay (ns) Site Resource ROUTE 144 7.878 OSC.OSC to R9C13C.CLK CLK_I_inferred_clock REG_DEL --- 0.955 R9C13C.CLK to R9C13C.Q0 SLICE_294 ROUTE 33 5.856 R9C13C.Q0 to R5C11A.A1 II_1/opcode_t1_29 CTOF_DEL --- 0.923 R5C11A.A1 to R5C11A.F1 II_1/alu/SLICE_436 ROUTE 2 3.386 R5C11A.F1 to R2C13D.B0 II_1/alu/un1_d_out126_0_a2_0_0 CTOOFX_DEL --- 1.359 R2C13D.B0 to R2C13D.OFX0 II_1/alu/un1_d_out126_0/SLICE_297 ROUTE 17 8.695 R2C13D.OFX0 to R5C10C.CLK II_1/alu/un1_d_out126_0 -------- 29.052 (11.1% logic, 88.9% route), 3 logic levels. Destination Clock Path iosc to II_1/imem/SLICE_158: Name Fanout Delay (ns) Site Resource ROUTE 144 7.878 OSC.OSC to R2C17B.CLK CLK_I_inferred_clock -------- 7.878 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 8.633ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q II_1/alu/d_out_1 (from II_1/alu/un1_d_out126_0 +) Destination: FF Data in II_1/imem/ptr1_t1_r_6 (to CLK_I_inferred_clock +) Delay: 18.636ns (29.8% logic, 70.2% route), 5 logic levels. Constraint Details: 18.636ns physical path delay II_1/alu/SLICE_189 to II_1/imem/SLICE_154 meets 48.875ns delay constraint less 21.174ns skew and 0.432ns DIN_SET requirement (totaling 27.269ns) by 8.633ns Physical Path Details: Data path II_1/alu/SLICE_189 to II_1/imem/SLICE_154: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.955 R5C9A.CLK to R5C9A.Q1 II_1/alu/SLICE_189 (from II_1/alu/un1_d_out126_0) ROUTE 1 6.800 R5C9A.Q1 to R5C14A.A1 II_1/alu_out_1 CTOF_DEL --- 0.923 R5C14A.A1 to R5C14A.F1 II_1/SLICE_275 ROUTE 6 6.279 R5C14A.F1 to R2C14B.B0 DIN_O_c_1 C0TOFCO_DE --- 2.064 R2C14B.B0 to R2C14B.FCO II_1/imem/SLICE_156 ROUTE 1 0.000 R2C14B.FCO to R2C14C.FCI II_1/imem/ptr1_t1_r_cry_2 FCITOFCO_D --- 0.317 R2C14C.FCI to R2C14C.FCO II_1/imem/SLICE_155 ROUTE 1 0.000 R2C14C.FCO to R2C14D.FCI II_1/imem/ptr1_t1_r_cry_4 FCITOF1_DE --- 1.298 R2C14D.FCI to R2C14D.F1 II_1/imem/SLICE_154 ROUTE 1 0.000 R2C14D.F1 to R2C14D.DI1 II_1/imem/ptr1_t1_r_s_6 (to CLK_I_inferred_clock) -------- 18.636 (29.8% logic, 70.2% route), 5 logic levels. Clock Skew Details: Source Clock Path iosc to II_1/alu/SLICE_189: Name Fanout Delay (ns) Site Resource ROUTE 144 7.878 OSC.OSC to R9C13C.CLK CLK_I_inferred_clock REG_DEL --- 0.955 R9C13C.CLK to R9C13C.Q0 SLICE_294 ROUTE 33 5.856 R9C13C.Q0 to R5C11A.A1 II_1/opcode_t1_29 CTOF_DEL --- 0.923 R5C11A.A1 to R5C11A.F1 II_1/alu/SLICE_436 ROUTE 2 3.386 R5C11A.F1 to R2C13D.B0 II_1/alu/un1_d_out126_0_a2_0_0 CTOOFX_DEL --- 1.359 R2C13D.B0 to R2C13D.OFX0 II_1/alu/un1_d_out126_0/SLICE_297 ROUTE 17 8.695 R2C13D.OFX0 to R5C9A.CLK II_1/alu/un1_d_out126_0 -------- 29.052 (11.1% logic, 88.9% route), 3 logic levels. Destination Clock Path iosc to II_1/imem/SLICE_154: Name Fanout Delay (ns) Site Resource ROUTE 144 7.878 OSC.OSC to R2C14D.CLK CLK_I_inferred_clock -------- 7.878 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 8.674ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q II_1/alu/d_out_1 (from II_1/alu/un1_d_out126_0 +) Destination: FF Data in II_1/imem/ptr0_t1_r_6 (to CLK_I_inferred_clock +) Delay: 18.595ns (29.9% logic, 70.1% route), 5 logic levels. Constraint Details: 18.595ns physical path delay II_1/alu/SLICE_189 to II_1/imem/SLICE_160 meets 48.875ns delay constraint less 21.174ns skew and 0.432ns DIN_SET requirement (totaling 27.269ns) by 8.674ns Physical Path Details: Data path II_1/alu/SLICE_189 to II_1/imem/SLICE_160: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.955 R5C9A.CLK to R5C9A.Q1 II_1/alu/SLICE_189 (from II_1/alu/un1_d_out126_0) ROUTE 1 6.800 R5C9A.Q1 to R5C14A.A1 II_1/alu_out_1 CTOF_DEL --- 0.923 R5C14A.A1 to R5C14A.F1 II_1/SLICE_275 ROUTE 6 6.238 R5C14A.F1 to R2C16B.A0 DIN_O_c_1 C0TOFCO_DE --- 2.064 R2C16B.A0 to R2C16B.FCO II_1/imem/SLICE_162 ROUTE 1 0.000 R2C16B.FCO to R2C16C.FCI II_1/imem/ptr0_t1_r_cry_2 FCITOFCO_D --- 0.317 R2C16C.FCI to R2C16C.FCO II_1/imem/SLICE_161 ROUTE 1 0.000 R2C16C.FCO to R2C16D.FCI II_1/imem/ptr0_t1_r_cry_4 FCITOF1_DE --- 1.298 R2C16D.FCI to R2C16D.F1 II_1/imem/SLICE_160 ROUTE 1 0.000 R2C16D.F1 to R2C16D.DI1 II_1/imem/ptr0_t1_r_s_6 (to CLK_I_inferred_clock) -------- 18.595 (29.9% logic, 70.1% route), 5 logic levels. Clock Skew Details: Source Clock Path iosc to II_1/alu/SLICE_189: Name Fanout Delay (ns) Site Resource ROUTE 144 7.878 OSC.OSC to R9C13C.CLK CLK_I_inferred_clock REG_DEL --- 0.955 R9C13C.CLK to R9C13C.Q0 SLICE_294 ROUTE 33 5.856 R9C13C.Q0 to R5C11A.A1 II_1/opcode_t1_29 CTOF_DEL --- 0.923 R5C11A.A1 to R5C11A.F1 II_1/alu/SLICE_436 ROUTE 2 3.386 R5C11A.F1 to R2C13D.B0 II_1/alu/un1_d_out126_0_a2_0_0 CTOOFX_DEL --- 1.359 R2C13D.B0 to R2C13D.OFX0 II_1/alu/un1_d_out126_0/SLICE_297 ROUTE 17 8.695 R2C13D.OFX0 to R5C9A.CLK II_1/alu/un1_d_out126_0 -------- 29.052 (11.1% logic, 88.9% route), 3 logic levels. Destination Clock Path iosc to II_1/imem/SLICE_160: Name Fanout Delay (ns) Site Resource ROUTE 144 7.878 OSC.OSC to R2C16D.CLK CLK_I_inferred_clock -------- 7.878 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 8.749ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q II_1/alu/d_out_2 (from II_1/alu/un1_d_out126_0 +) Destination: FF Data in II_1/imem/ptr0_t1_r_8 (to CLK_I_inferred_clock +) Delay: 18.520ns (30.3% logic, 69.7% route), 6 logic levels. Constraint Details: 18.520ns physical path delay II_1/alu/SLICE_190 to II_1/imem/SLICE_159 meets 48.875ns delay constraint less 21.174ns skew and 0.432ns DIN_SET requirement (totaling 27.269ns) by 8.749ns Physical Path Details: Data path II_1/alu/SLICE_190 to II_1/imem/SLICE_159: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.955 R5C10C.CLK to R5C10C.Q0 II_1/alu/SLICE_190 (from II_1/alu/un1_d_out126_0) ROUTE 1 6.969 R5C10C.Q0 to R5C15A.A0 II_1/alu_out_2 CTOF_DEL --- 0.923 R5C15A.A0 to R5C15A.F0 II_1/SLICE_276 ROUTE 6 5.946 R5C15A.F0 to R2C16B.A1 DIN_O_c_2 C1TOFCO_DE --- 1.795 R2C16B.A1 to R2C16B.FCO II_1/imem/SLICE_162 ROUTE 1 0.000 R2C16B.FCO to R2C16C.FCI II_1/imem/ptr0_t1_r_cry_2 FCITOFCO_D --- 0.317 R2C16C.FCI to R2C16C.FCO II_1/imem/SLICE_161 ROUTE 1 0.000 R2C16C.FCO to R2C16D.FCI II_1/imem/ptr0_t1_r_cry_4 FCITOFCO_D --- 0.317 R2C16D.FCI to R2C16D.FCO II_1/imem/SLICE_160 ROUTE 1 0.000 R2C16D.FCO to R2C17A.FCI II_1/imem/ptr0_t1_r_cry_6 FCITOF1_DE --- 1.298 R2C17A.FCI to R2C17A.F1 II_1/imem/SLICE_159 ROUTE 1 0.000 R2C17A.F1 to R2C17A.DI1 II_1/imem/ptr0_t1_r_s_8 (to CLK_I_inferred_clock) -------- 18.520 (30.3% logic, 69.7% route), 6 logic levels. Clock Skew Details: Source Clock Path iosc to II_1/alu/SLICE_190: Name Fanout Delay (ns) Site Resource ROUTE 144 7.878 OSC.OSC to R9C13C.CLK CLK_I_inferred_clock REG_DEL --- 0.955 R9C13C.CLK to R9C13C.Q0 SLICE_294 ROUTE 33 5.856 R9C13C.Q0 to R5C11A.A1 II_1/opcode_t1_29 CTOF_DEL --- 0.923 R5C11A.A1 to R5C11A.F1 II_1/alu/SLICE_436 ROUTE 2 3.386 R5C11A.F1 to R2C13D.B0 II_1/alu/un1_d_out126_0_a2_0_0 CTOOFX_DEL --- 1.359 R2C13D.B0 to R2C13D.OFX0 II_1/alu/un1_d_out126_0/SLICE_297 ROUTE 17 8.695 R2C13D.OFX0 to R5C10C.CLK II_1/alu/un1_d_out126_0 -------- 29.052 (11.1% logic, 88.9% route), 3 logic levels. Destination Clock Path iosc to II_1/imem/SLICE_159: Name Fanout Delay (ns) Site Resource ROUTE 144 7.878 OSC.OSC to R2C17A.CLK CLK_I_inferred_clock -------- 7.878 (0.0% logic, 100.0% route), 0 logic levels. Report: 24.534MHz is the maximum frequency for this preference. Report Summary -------------- ---------------------------------------------------------------------------- Preference | Constraint| Actual|Levels ---------------------------------------------------------------------------- | | | FREQUENCY NET "CLK_I_inferred_clock" | | | 20.460000 MHz ; | 20.460 MHz| 24.534 MHz| 7 | | | ---------------------------------------------------------------------------- All preferences were met. Clock Domains Analysis ------------------------ Found 2 clocks: Clock Domain: CLK_I_inferred_clock Source: iosc.OSC Loads: 144 Covered under: FREQUENCY NET "CLK_I_inferred_clock" 20.460000 MHz ; Data transfers from: Clock Domain: II_1/alu/un1_d_out126_0 Source: II_1/alu/un1_d_out126_0/SLICE_297.OFX0 Covered under: FREQUENCY NET "CLK_I_inferred_clock" 20.460000 MHz ; Transfers: 32 Clock Domain: II_1/alu/un1_d_out126_0 Source: II_1/alu/un1_d_out126_0/SLICE_297.OFX0 Loads: 17 No transfer within this clock domain is found Timing summary (Setup): --------------- Timing errors: 0 Score: 0 Cumulative negative slack: 0 Constraints cover 22451 paths, 1 nets, and 3445 connections (73.1% coverage) -------------------------------------------------------------------------------- Lattice TRACE Report - Hold, Version Diamond_1.4_Production (87) Sun Apr 07 08:52:00 2013 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2011 Lattice Semiconductor Corporation, All rights reserved. Report Information ------------------ Command line: trce -v 10 -gt -sethld -sp 1 -sphld m -o pnutdsp_lattice_pnutdsp_lattice.twr pnutdsp_lattice_pnutdsp_lattice.ncd pnutdsp_lattice_pnutdsp_lattice.prf Design file: pnutdsp_lattice_pnutdsp_lattice.ncd Preference file: pnutdsp_lattice_pnutdsp_lattice.prf Device,speed: LCMXO2-1200ZE,m Report level: verbose report, limited to 10 items per preference -------------------------------------------------------------------------------- Preference Summary FREQUENCY NET "CLK_I_inferred_clock" 20.460000 MHz (0 errors) 4096 items scored, 0 timing errors detected. BLOCK ASYNCPATHS BLOCK RESETPATHS -------------------------------------------------------------------------------- ================================================================================ Preference: FREQUENCY NET "CLK_I_inferred_clock" 20.460000 MHz ; 4096 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- Passed: The following path meets requirements by 0.856ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q II_1/imem/cnt_r_21 (from CLK_I_inferred_clock +) Destination: FF Data in II_1/imem/cnt_r_21 (to CLK_I_inferred_clock +) Delay: 0.824ns (55.3% logic, 44.7% route), 2 logic levels. Constraint Details: 0.824ns physical path delay II_1/imem/SLICE_169 to II_1/imem/SLICE_169 meets -0.032ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.032ns) by 0.856ns Physical Path Details: Data path II_1/imem/SLICE_169 to II_1/imem/SLICE_169: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.257 R10C15D.CLK to R10C15D.Q0 II_1/imem/SLICE_169 (from CLK_I_inferred_clock) ROUTE 3 0.368 R10C15D.Q0 to R10C15D.A0 II_1/imem/cnt_r_21 CTOF_DEL --- 0.199 R10C15D.A0 to R10C15D.F0 II_1/imem/SLICE_169 ROUTE 1 0.000 R10C15D.F0 to R10C15D.DI0 II_1/imem/cnt_r_s_21 (to CLK_I_inferred_clock) -------- 0.824 (55.3% logic, 44.7% route), 2 logic levels. Clock Skew Details: Source Clock Path iosc to II_1/imem/SLICE_169: Name Fanout Delay (ns) Site Resource ROUTE 144 2.474 OSC.OSC to R10C15D.CLK CLK_I_inferred_clock -------- 2.474 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path iosc to II_1/imem/SLICE_169: Name Fanout Delay (ns) Site Resource ROUTE 144 2.474 OSC.OSC to R10C15D.CLK CLK_I_inferred_clock -------- 2.474 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.856ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q II_1/imem/cnt_r_16 (from CLK_I_inferred_clock +) Destination: FF Data in II_1/imem/cnt_r_16 (to CLK_I_inferred_clock +) Delay: 0.824ns (55.3% logic, 44.7% route), 2 logic levels. Constraint Details: 0.824ns physical path delay II_1/imem/SLICE_172 to II_1/imem/SLICE_172 meets -0.032ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.032ns) by 0.856ns Physical Path Details: Data path II_1/imem/SLICE_172 to II_1/imem/SLICE_172: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.257 R10C15A.CLK to R10C15A.Q1 II_1/imem/SLICE_172 (from CLK_I_inferred_clock) ROUTE 3 0.368 R10C15A.Q1 to R10C15A.A1 II_1/imem/cnt_r_16 CTOF_DEL --- 0.199 R10C15A.A1 to R10C15A.F1 II_1/imem/SLICE_172 ROUTE 1 0.000 R10C15A.F1 to R10C15A.DI1 II_1/imem/cnt_r_s_16 (to CLK_I_inferred_clock) -------- 0.824 (55.3% logic, 44.7% route), 2 logic levels. Clock Skew Details: Source Clock Path iosc to II_1/imem/SLICE_172: Name Fanout Delay (ns) Site Resource ROUTE 144 2.474 OSC.OSC to R10C15A.CLK CLK_I_inferred_clock -------- 2.474 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path iosc to II_1/imem/SLICE_172: Name Fanout Delay (ns) Site Resource ROUTE 144 2.474 OSC.OSC to R10C15A.CLK CLK_I_inferred_clock -------- 2.474 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.856ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q II_1/imem/cnt_r_10 (from CLK_I_inferred_clock +) Destination: FF Data in II_1/imem/cnt_r_10 (to CLK_I_inferred_clock +) Delay: 0.824ns (55.3% logic, 44.7% route), 2 logic levels. Constraint Details: 0.824ns physical path delay II_1/imem/SLICE_175 to II_1/imem/SLICE_175 meets -0.032ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.032ns) by 0.856ns Physical Path Details: Data path II_1/imem/SLICE_175 to II_1/imem/SLICE_175: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.257 R10C14B.CLK to R10C14B.Q1 II_1/imem/SLICE_175 (from CLK_I_inferred_clock) ROUTE 3 0.368 R10C14B.Q1 to R10C14B.A1 II_1/imem/cnt_r_10 CTOF_DEL --- 0.199 R10C14B.A1 to R10C14B.F1 II_1/imem/SLICE_175 ROUTE 1 0.000 R10C14B.F1 to R10C14B.DI1 II_1/imem/cnt_r_s_10 (to CLK_I_inferred_clock) -------- 0.824 (55.3% logic, 44.7% route), 2 logic levels. Clock Skew Details: Source Clock Path iosc to II_1/imem/SLICE_175: Name Fanout Delay (ns) Site Resource ROUTE 144 2.474 OSC.OSC to R10C14B.CLK CLK_I_inferred_clock -------- 2.474 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path iosc to II_1/imem/SLICE_175: Name Fanout Delay (ns) Site Resource ROUTE 144 2.474 OSC.OSC to R10C14B.CLK CLK_I_inferred_clock -------- 2.474 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.856ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q II_1/imem/cnt_r_3 (from CLK_I_inferred_clock +) Destination: FF Data in II_1/imem/cnt_r_3 (to CLK_I_inferred_clock +) Delay: 0.824ns (55.3% logic, 44.7% route), 2 logic levels. Constraint Details: 0.824ns physical path delay II_1/imem/SLICE_178 to II_1/imem/SLICE_178 meets -0.032ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.032ns) by 0.856ns Physical Path Details: Data path II_1/imem/SLICE_178 to II_1/imem/SLICE_178: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.257 R10C13C.CLK to R10C13C.Q0 II_1/imem/SLICE_178 (from CLK_I_inferred_clock) ROUTE 3 0.368 R10C13C.Q0 to R10C13C.A0 II_1/imem/cnt_r_3 CTOF_DEL --- 0.199 R10C13C.A0 to R10C13C.F0 II_1/imem/SLICE_178 ROUTE 1 0.000 R10C13C.F0 to R10C13C.DI0 II_1/imem/cnt_r_s_3 (to CLK_I_inferred_clock) -------- 0.824 (55.3% logic, 44.7% route), 2 logic levels. Clock Skew Details: Source Clock Path iosc to II_1/imem/SLICE_178: Name Fanout Delay (ns) Site Resource ROUTE 144 2.474 OSC.OSC to R10C13C.CLK CLK_I_inferred_clock -------- 2.474 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path iosc to II_1/imem/SLICE_178: Name Fanout Delay (ns) Site Resource ROUTE 144 2.474 OSC.OSC to R10C13C.CLK CLK_I_inferred_clock -------- 2.474 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.856ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q II_1/imem/cnt_r_17 (from CLK_I_inferred_clock +) Destination: FF Data in II_1/imem/cnt_r_17 (to CLK_I_inferred_clock +) Delay: 0.824ns (55.3% logic, 44.7% route), 2 logic levels. Constraint Details: 0.824ns physical path delay II_1/imem/SLICE_171 to II_1/imem/SLICE_171 meets -0.032ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.032ns) by 0.856ns Physical Path Details: Data path II_1/imem/SLICE_171 to II_1/imem/SLICE_171: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.257 R10C15B.CLK to R10C15B.Q0 II_1/imem/SLICE_171 (from CLK_I_inferred_clock) ROUTE 3 0.368 R10C15B.Q0 to R10C15B.A0 II_1/imem/cnt_r_17 CTOF_DEL --- 0.199 R10C15B.A0 to R10C15B.F0 II_1/imem/SLICE_171 ROUTE 1 0.000 R10C15B.F0 to R10C15B.DI0 II_1/imem/cnt_r_s_17 (to CLK_I_inferred_clock) -------- 0.824 (55.3% logic, 44.7% route), 2 logic levels. Clock Skew Details: Source Clock Path iosc to II_1/imem/SLICE_171: Name Fanout Delay (ns) Site Resource ROUTE 144 2.474 OSC.OSC to R10C15B.CLK CLK_I_inferred_clock -------- 2.474 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path iosc to II_1/imem/SLICE_171: Name Fanout Delay (ns) Site Resource ROUTE 144 2.474 OSC.OSC to R10C15B.CLK CLK_I_inferred_clock -------- 2.474 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.856ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q II_1/imem/cnt_r_28 (from CLK_I_inferred_clock +) Destination: FF Data in II_1/imem/cnt_r_28 (to CLK_I_inferred_clock +) Delay: 0.824ns (55.3% logic, 44.7% route), 2 logic levels. Constraint Details: 0.824ns physical path delay II_1/imem/SLICE_166 to II_1/imem/SLICE_166 meets -0.032ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.032ns) by 0.856ns Physical Path Details: Data path II_1/imem/SLICE_166 to II_1/imem/SLICE_166: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.257 R10C16C.CLK to R10C16C.Q1 II_1/imem/SLICE_166 (from CLK_I_inferred_clock) ROUTE 3 0.368 R10C16C.Q1 to R10C16C.A1 II_1/imem/cnt_r_28 CTOF_DEL --- 0.199 R10C16C.A1 to R10C16C.F1 II_1/imem/SLICE_166 ROUTE 1 0.000 R10C16C.F1 to R10C16C.DI1 II_1/imem/cnt_r_s_28 (to CLK_I_inferred_clock) -------- 0.824 (55.3% logic, 44.7% route), 2 logic levels. Clock Skew Details: Source Clock Path iosc to II_1/imem/SLICE_166: Name Fanout Delay (ns) Site Resource ROUTE 144 2.474 OSC.OSC to R10C16C.CLK CLK_I_inferred_clock -------- 2.474 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path iosc to II_1/imem/SLICE_166: Name Fanout Delay (ns) Site Resource ROUTE 144 2.474 OSC.OSC to R10C16C.CLK CLK_I_inferred_clock -------- 2.474 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.856ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q II_1/imem/cnt_r_14 (from CLK_I_inferred_clock +) Destination: FF Data in II_1/imem/cnt_r_14 (to CLK_I_inferred_clock +) Delay: 0.824ns (55.3% logic, 44.7% route), 2 logic levels. Constraint Details: 0.824ns physical path delay II_1/imem/SLICE_173 to II_1/imem/SLICE_173 meets -0.032ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.032ns) by 0.856ns Physical Path Details: Data path II_1/imem/SLICE_173 to II_1/imem/SLICE_173: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.257 R10C14D.CLK to R10C14D.Q1 II_1/imem/SLICE_173 (from CLK_I_inferred_clock) ROUTE 3 0.368 R10C14D.Q1 to R10C14D.A1 II_1/imem/cnt_r_14 CTOF_DEL --- 0.199 R10C14D.A1 to R10C14D.F1 II_1/imem/SLICE_173 ROUTE 1 0.000 R10C14D.F1 to R10C14D.DI1 II_1/imem/cnt_r_s_14 (to CLK_I_inferred_clock) -------- 0.824 (55.3% logic, 44.7% route), 2 logic levels. Clock Skew Details: Source Clock Path iosc to II_1/imem/SLICE_173: Name Fanout Delay (ns) Site Resource ROUTE 144 2.474 OSC.OSC to R10C14D.CLK CLK_I_inferred_clock -------- 2.474 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path iosc to II_1/imem/SLICE_173: Name Fanout Delay (ns) Site Resource ROUTE 144 2.474 OSC.OSC to R10C14D.CLK CLK_I_inferred_clock -------- 2.474 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.856ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q II_1/imem/cnt_r_20 (from CLK_I_inferred_clock +) Destination: FF Data in II_1/imem/cnt_r_20 (to CLK_I_inferred_clock +) Delay: 0.824ns (55.3% logic, 44.7% route), 2 logic levels. Constraint Details: 0.824ns physical path delay II_1/imem/SLICE_170 to II_1/imem/SLICE_170 meets -0.032ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.032ns) by 0.856ns Physical Path Details: Data path II_1/imem/SLICE_170 to II_1/imem/SLICE_170: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.257 R10C15C.CLK to R10C15C.Q1 II_1/imem/SLICE_170 (from CLK_I_inferred_clock) ROUTE 3 0.368 R10C15C.Q1 to R10C15C.A1 II_1/imem/cnt_r_20 CTOF_DEL --- 0.199 R10C15C.A1 to R10C15C.F1 II_1/imem/SLICE_170 ROUTE 1 0.000 R10C15C.F1 to R10C15C.DI1 II_1/imem/cnt_r_s_20 (to CLK_I_inferred_clock) -------- 0.824 (55.3% logic, 44.7% route), 2 logic levels. Clock Skew Details: Source Clock Path iosc to II_1/imem/SLICE_170: Name Fanout Delay (ns) Site Resource ROUTE 144 2.474 OSC.OSC to R10C15C.CLK CLK_I_inferred_clock -------- 2.474 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path iosc to II_1/imem/SLICE_170: Name Fanout Delay (ns) Site Resource ROUTE 144 2.474 OSC.OSC to R10C15C.CLK CLK_I_inferred_clock -------- 2.474 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.856ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q II_1/imem/cnt_r_26 (from CLK_I_inferred_clock +) Destination: FF Data in II_1/imem/cnt_r_26 (to CLK_I_inferred_clock +) Delay: 0.824ns (55.3% logic, 44.7% route), 2 logic levels. Constraint Details: 0.824ns physical path delay II_1/imem/SLICE_167 to II_1/imem/SLICE_167 meets -0.032ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.032ns) by 0.856ns Physical Path Details: Data path II_1/imem/SLICE_167 to II_1/imem/SLICE_167: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.257 R10C16B.CLK to R10C16B.Q1 II_1/imem/SLICE_167 (from CLK_I_inferred_clock) ROUTE 3 0.368 R10C16B.Q1 to R10C16B.A1 II_1/imem/cnt_r_26 CTOF_DEL --- 0.199 R10C16B.A1 to R10C16B.F1 II_1/imem/SLICE_167 ROUTE 1 0.000 R10C16B.F1 to R10C16B.DI1 II_1/imem/cnt_r_s_26 (to CLK_I_inferred_clock) -------- 0.824 (55.3% logic, 44.7% route), 2 logic levels. Clock Skew Details: Source Clock Path iosc to II_1/imem/SLICE_167: Name Fanout Delay (ns) Site Resource ROUTE 144 2.474 OSC.OSC to R10C16B.CLK CLK_I_inferred_clock -------- 2.474 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path iosc to II_1/imem/SLICE_167: Name Fanout Delay (ns) Site Resource ROUTE 144 2.474 OSC.OSC to R10C16B.CLK CLK_I_inferred_clock -------- 2.474 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.856ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q II_1/imem/cnt_r_27 (from CLK_I_inferred_clock +) Destination: FF Data in II_1/imem/cnt_r_27 (to CLK_I_inferred_clock +) Delay: 0.824ns (55.3% logic, 44.7% route), 2 logic levels. Constraint Details: 0.824ns physical path delay II_1/imem/SLICE_166 to II_1/imem/SLICE_166 meets -0.032ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.032ns) by 0.856ns Physical Path Details: Data path II_1/imem/SLICE_166 to II_1/imem/SLICE_166: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.257 R10C16C.CLK to R10C16C.Q0 II_1/imem/SLICE_166 (from CLK_I_inferred_clock) ROUTE 3 0.368 R10C16C.Q0 to R10C16C.A0 II_1/imem/cnt_r_27 CTOF_DEL --- 0.199 R10C16C.A0 to R10C16C.F0 II_1/imem/SLICE_166 ROUTE 1 0.000 R10C16C.F0 to R10C16C.DI0 II_1/imem/cnt_r_s_27 (to CLK_I_inferred_clock) -------- 0.824 (55.3% logic, 44.7% route), 2 logic levels. Clock Skew Details: Source Clock Path iosc to II_1/imem/SLICE_166: Name Fanout Delay (ns) Site Resource ROUTE 144 2.474 OSC.OSC to R10C16C.CLK CLK_I_inferred_clock -------- 2.474 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path iosc to II_1/imem/SLICE_166: Name Fanout Delay (ns) Site Resource ROUTE 144 2.474 OSC.OSC to R10C16C.CLK CLK_I_inferred_clock -------- 2.474 (0.0% logic, 100.0% route), 0 logic levels. Report Summary -------------- ---------------------------------------------------------------------------- Preference(MIN Delays) | Constraint| Actual|Levels ---------------------------------------------------------------------------- | | | FREQUENCY NET "CLK_I_inferred_clock" | | | 20.460000 MHz ; | -| -| 2 | | | ---------------------------------------------------------------------------- All preferences were met. Clock Domains Analysis ------------------------ Found 2 clocks: Clock Domain: CLK_I_inferred_clock Source: iosc.OSC Loads: 144 Covered under: FREQUENCY NET "CLK_I_inferred_clock" 20.460000 MHz ; Data transfers from: Clock Domain: II_1/alu/un1_d_out126_0 Source: II_1/alu/un1_d_out126_0/SLICE_297.OFX0 Covered under: FREQUENCY NET "CLK_I_inferred_clock" 20.460000 MHz ; Transfers: 32 Clock Domain: II_1/alu/un1_d_out126_0 Source: II_1/alu/un1_d_out126_0/SLICE_297.OFX0 Loads: 17 No transfer within this clock domain is found Timing summary (Hold): --------------- Timing errors: 0 Score: 0 Cumulative negative slack: 0 Constraints cover 22451 paths, 1 nets, and 3444 connections (73.0% coverage) Timing summary (Setup and Hold): --------------- Timing errors: 0 (setup), 0 (hold) Score: 0 (setup), 0 (hold) Cumulative negative slack: 0 (0+0) --------------------------------------------------------------------------------I'll post more code soon