High Frequency Coordinated Pulses

StephenMoore · 2012-04-13 19:39

A while back forum members solved the counter jitter problem when generating arbitary pulse lengths up to 300kHz (this was at 50% duty cycle). Now I am trying to pulse a pin for short duration (like 40 clock ticks), wait a time period, pulse a second pin for short duration, wait another period and repeat the cycle

Here is my program which crudely works but I do not know why it does.

The code in :loop2 handles all the delay timing but only works when I swap the pulse on duration with the pulse off delays. Can somebody with a o-scope try this and see if it makes any sense?

The user interface works with PST and enter a "0" to get the pulse menu (otherwise it takes a frequency for 50% duty cycle operation as input).

Regards,

sm

kuroneko · 2012-04-13 19:56

:loop2        xor       outa, Apin               ' this works  but doesn't make any sense
              waitcnt   curTime, BpinDelay       ' to me
              xor       outa, Apin
              waitcnt   curTime, pulseLen
              xor       outa, Bpin
              waitcnt   curTime, ApinDelay
              xor       outa, Bpin
              waitcnt   curTime, pulseLen
              jmp       #:loop2

Makes perfect sense. curTime is set for pulseLen in advance, i.e. we switch on A and wait until curTime is reached (which is pulseLen from now). At the same time we advance the target by BpinDelay (A_off -> B_on). Then A is switched off. We wait again, after BpinDelay we switch on B. Maybe it's simply due to the fact that waitcnt in PASM works slightly different from the SPIN version.

That said, you should restructure your loop so that the xor always follows waitcnt otherwise the jump insn introduces an error of 4 cycles. HTH

StephenMoore · 2012-04-13 21:49

I guess it was my understanding of waitcnt that was bogus... delta is added to target after system clock has advanced to target value.

Thanks for the scrub down.

I am working on a way to handle this same problem using ctra and ctrb. In other words, synching ctra to ctrb each with its own adjustable duty cycle. Would waitpe be the way to go?

My goal is to have very high frequency pulses (200kHz < freq < 2MHz) at less than 50% duty cycle. This would give jitter-free independently adjustable pulse widths and delays between pulses without all of the waitcnt business on two separate pins. It might also allow me to better utilize the power of the Propeller.

This may seem obscure but we are looking at ways to optimize control for half-bridge switch circuits.

Regards,

sm

kuroneko · 2012-04-13 22:51

StephenMoore wrote: »

I am working on a way to handle this same problem using ctra and ctrb. In other words, synching ctra to ctrb each with its own adjustable duty cycle.

So same behaviour but with counters? How do you plan to adjust the duty cycle? The counter DUTY mode itself only generates pulses one clock cycle in length.

Video h/w usage may be something else to consider.

High Frequency Coordinated Pulses

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