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Solutions for adding SRAM to your BASIC Stamp circuits — Parallax Forums

Solutions for adding SRAM to your BASIC Stamp circuits

Andy FoxAndy Fox Posts: 46
edited 2008-01-29 18:09 in BASIC Stamp
Hello, everyone. I've been experimenting recently on ways of adding SRAM to my BASIC Stamp projects for storing data. Anyone who needs to store some temporary volitile data and are concerned with the 1,000,000 rewrite limits of the BASIC Stamp's EEPROM may find this topic useful.

When I went looking for existing SRAM module boards the only one I found was something called "RAM Pack B" which is now discontinued, however I did find a site in Europe apparently selling them for $40. Anyhow, with this limited availability I decided to make my own.

I tried two different approaches:

SRAM circuit #1 is the simplest from a building and coding standpoint and is ideal for people who need to store a small amount of data and speed is not a priority. It uses an array of Phillips PCF8570 256x8 SRAM chips. My circuit used 4 of them giving a total of 1k of SRAM. The chips are I2C so only two pins from a BASIC Stamp are needed. Speeds: 22.56 read-writes/sec (BS2), 76.42 read-writes/sec (BS2p), and a sizzling 426.67 read-writes/sec (BS2p using native I2C commands). To my surprise this actually out-performed my SRAM circuit #2 (see below).

users.minn.net/landru/pub/sram.jpg

The downfalls with this method are SRAM size limitations and (unless you're using a BS2p) speed. You can wire up to 16 PCF8570's with no additional logic chips, which will give you 4k to work with, but that's a lot of chips! smile.gif

SRAM circuit #2 is more complex, but offers better speed and much more SRAM expansion. This circuit uses three 74HC299's, one 74HC00, and any of a dozen different SRAM chips you choose (6116, 2114, 6264, 71256, etc). My circuit uses a 7164 8192x8 SRAM chip. I got the schematic and theory of operation for this circuit off of this website: www.captain.at/electronics/pic-ram/ (second schematic). Speeds 99.3 read-writes/sec (BS2), 287.4 read-writes/sec (BS2p).

users.minn.net/landru/pub/sram2.jpg

The wiring for this circuit allows up to 64k of SRAM to be addressed (16 address lines).
This circuit does, however, use 6 I/O pins instead of just the 2 used earlier, so that and the amount of wiring are the trade-off's.

A note on my speed numbers: For each circuit I had a program to "test" the memory by writing various values to it and then reading them back in to confirm the write was successful. My "read-writes/sec" numbers indicate how many memory addresses were able to be written to and read from in one second.

Anyhow, thought I'd share the knowledge with everyone. If anyone would like the BASIC code to access the memory in these modules I can provide it.

Post Edited (Andy Fox) : 11/26/2007 4:23:47 PM GMT

Comments

  • Bruce BatesBruce Bates Posts: 3,045
    edited 2007-11-26 09:42
    Andy -

    You may wish to look at the non-volatile FRAM memory offered by RAMTRON. The re-write limitations are substantially higher, and there are no wait periods required for memory writes. Here is a link to their web site: http://www.ramtron.com/ .

    Regards,

    Bruce Bates

    ▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
  • Andy FoxAndy Fox Posts: 46
    edited 2007-11-26 16:33
    Thanks for the link. I did look into FRAM as a solution to EEPROM but it was my understanding FRAM also had similar read-write limits. Maybe these guys have overcome that. Can't really find any of their chips for sale anywhere though, so I wonder how expensive they are.

    As for speed, it's pretty much a moot point with the BASIC Stamps. Even with the speedy BS2p, the *fastest* it can possibly access a SRAM chip (using my circuit) is around 800ns.
  • Mike GreenMike Green Posts: 23,101
    edited 2007-11-26 16:47
    The main advantage of the FRAM is that the write time is the same as the read time and they both run as fast as the I2C/SPI can go.

    FRAM is different from EEPROM in that, as I understand it, the read cycle is destructive and the data has to be written back to the
    FRAM array. This is automatic. Therefore, the limit on the number of write cycles also applies to read cycles, but the limit is much
    higher than that for EEPROMs.
  • Andy FoxAndy Fox Posts: 46
    edited 2008-01-29 18:09
    Hey, everyone! I have an update on my SRAM project.

    I recently got my hands on some PCF8574 I2C 8-bit I/O expanders and re-did my second circuit to access the 8k SRAM chip via I2C protocol rather than the slightly more cumbersome shift registers. I replaced the three 74HC299's with three PCF8574's. The 74HC00 chip is no longer needed:

    users.minn.net/landru/pub/sram3.jpg

    As it turns out the access time is nearly identical when using a BS2p with built-in I2C commands, coming in at 256 read/write operations/sec, just a hair slower than using the SHIFTIN/SHIFTOUT commands.

    The advantage is that this circuit only requires 4 I/O lines from the BASIC Stamp instead of the previous 6. Also the wiring is slightly less messy. The disadvantage is that PCF8574's are rarer and more expensive than the 74HC299's, and unless you are using a BS2p with built-in I2C, you won't get the speed advantage and may as well go with the shift registers.

    Hey--it's a great way to add a ton of scratch pad memory or video/character RAM to your circuits (which is what I originally started in on this for)!

    Again, if anyone wants exact schematics or source code let me know.
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