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Use of a Propeller chip to be a Address counter to a High-speed 32K x 8bit SRAM. — Parallax Forums

Use of a Propeller chip to be a Address counter to a High-speed 32K x 8bit SRAM.

LobLob Posts: 4
edited 2007-11-21 14:29 in Propeller 1
Newbee questions about the Propeller.

Use of a Propeller chip to be a Address counter to a High-speed 32K x 8bit SRAM.

Address Inputs A0 to A14 for the SRAM 15 ns. I need to use 15 I/O ports for the 15 adresslines.
Propeller chip will more or less be a binary counter.

Must use Assembly since the speed must be more than 20Mhz· Write to Sram.· Read from Sram much slower.
Have follow DeSilva excellent AssemblyTutorial.· I can adress up to $ 1FF ( Dec 511 ) if i address more then a got a error Register/Constant
cannot exceed $ 1FF any tip or solution do i have to use more cogs ?

Thanks in advance
Lob

Comments

  • hippyhippy Posts: 1,981
    edited 2007-11-20 19:44
    Presumably you have an instruction similar to "mov adr,#$1FF" and you're trying to use "mov adr,#$200" ?

    Immediate addressing only supports $000 to $1FF, after that you need to store numbers in a 'variable'

    DAT

    org 0
    mov adr,myVar
    add myVar,#1
    :
    myVar long $200
  • LobLob Posts: 4
    edited 2007-11-20 20:45
    Thanks Hippy

    ( Presumably you have an instruction similar to "mov adr,#$1FF" and you're trying to use "mov adr,#$200" ? )

    Yes it is exactly what i do and got the error Register/Constant

    Thanks again hippy

    Lob
  • AleAle Posts: 2,363
    edited 2007-11-20 21:15
    The propeller is not fast enough to change the addresses at 15 ns. Maybe you could use some cascaded 74act393 or a cpld (I go for the latter, due to the flexibility, but the other is just simpler), if you are planning on generating all addresses between 0000 and 7fff. To read slowly and to process the data, you could then use the propeller. .
  • LobLob Posts: 4
    edited 2007-11-20 21:51
    Thanks Ale

    My intention is to generate all addresses between 0000 and 7fff with the Propeller i aware that i could use some Hc chips ie 4040 as adress counter for the Sram.
    but if i am able to use the propeller chip i can save a some counter chips and logic chips and the same time i can controll the output from the Sram with the propeller.
    The output will go to a Usb chip. Ftdi 245
    Re speed i belive i can a least adress the Sram with 20 mhz to 30 Mhz with propeller.


    Thanks again Ale

    Lob
  • deSilvadeSilva Posts: 2,967
    edited 2007-11-21 01:41
    Ale said...
    The propeller is not fast enough to change the addresses at 15 ns.
    True, but that will be no issue! When writing to the SRAM you set all information in one OUTA-instruction (address, data and write-strobe) - but maybe OE or CS has to be delayed just a little bit to guarantee stable address and data..... When reading you INA during the next instruction, which is 50 ns later. The data is stable as long as the address does not change and OE and/or CS are reset... There are some "modes" you can work in.

    But to my opinion there is the need for at least 3 instructions per access, so a true "High Speed" SRAM (10...20ns) will be of no advantage... a 50 ns SRAM will be fine...
  • AleAle Posts: 2,363
    edited 2007-11-21 06:25
    deSilva: That is exactly why I suggested another method, if speed is paramount.
    But you can generate a clock to drive the counters with the propeller to write to the SRAM (when you input data fast enough)... and later drive it slower to transfer the data, and have another in to clear the counters. You will need 2 74act393 (or abt or another fast enough), they are not difficult to work with, 8 bits of output per chip smile.gif
  • deSilvadeSilva Posts: 2,967
    edited 2007-11-21 08:27
    Yopu will only get some "burst improvement" as you are limited to an "unrolled loop"
    OUTA x
    OUTA x
    OUTA x
    ....
    where the output also strobes the counter - with some delay (of - say 25 ns).
    It depends what you want to do with that data...
    There was a nice idea of simulating DMA" in one thread the other day, I liked very much (and commented to)...
  • AleAle Posts: 2,363
    edited 2007-11-21 10:14
    There is another possibility, using just one counter (one 74xx393). High addresses are generated with the propeller, and a fast clock to drive the counter, so there is 256 fast cycles between high address changes, that may work smile.gif, you save some 6 pins (one clock and one clear are still needed).
  • LobLob Posts: 4
    edited 2007-11-21 11:27
    Thanks Ale / deSilva

    The propeller chip will not write to Sram an 8 bit A/D will sample and write to Sram output from Sram go to Usb controller Ftdi 245
    the intention with the propeller is to be a address counter for Sram a clock for the A/D , propeller will also handle Write/Read , Output enable for Sram and
    controll the data flow from Sram to Usb by TXE, Wr on Ftdi chip .
    Presently it is no running on breadbord with 4040 adresscounter and some logic chips
    With the propeller chip the construction will only be 4 chips A/D , Sram, propeller and Usb. Except analog input to the A/D

    Final project Oscilloscope.

    I am now struggling with the output speed from propeller for the adresscounter, any idea best way to get max output speed for the adresscounter
    addresses between 0000 and 7fff


    Thanks again Ale / deSilva

    Lob
  • AleAle Posts: 2,363
    edited 2007-11-21 12:12
    Lob, I sort of did the same, but ended using a cpld. A Xilinx XC9536. They are cheap, and easy to program, even from linux (my dev platform of choice, till I can move everything to Mac of course), and fast.

    You want to get 60 MSPS, sort of, no ?, in 32 kb chunks and later send that via USB, so reading chunks of 256 or more bytes at once are desired.

    CE and WE can be tied to ground (AFAIK) and you can change addresses and the memory will be writable after the addresses settle, some xx ns, depending on the speed. That would reduce the need to toggle lines.
    To read, you can do it slower, and IF the ADC supports tri-state outputs (very important), you do not need any buffers between the ADC and the FTDI.
    Go for the just one counter for lower addresses, and test how reliable direct write (without *CS, *WE toggling) works.

    The prop cannot generate addresses that fast (15ns), because the outputs are or'ed together, so if you interleave 4 COGs for instance, when one output is high, there is no way to make it 0.... but now that I think of it... maybe the video generator can be used to "fake" a counter with 8 outputs... that leaves the slow addresses to be done by soft... yes yes that could definitely work !!! Try it, did you get how ?, investigate it, and later, tell me how it works smile.gif

    Gru
  • DroneDrone Posts: 433
    edited 2007-11-21 14:29
    Lob, bus converters are often done with CPLDs ("Complex" Programmable Logic Devices). Have a look at www.xilinx.com. Xilinx has the 9500 series and CoolRunnerII CPLDs. There's a special on the CoolRunnerII development X-Board for $25 USD (normally $50 USD). The Xilinx WebPack dev software is available free for download (big file size); includes a simulator if you don't want to buy the cheap dev board.
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