Assume we use I/O 8..23 as address register, and some other I/Os 0...7 as (masks!) MEMRD and DMAWR
MOV rep, #blcksize
MOV addr, startaddr
SHL addr, #8
OR addr, #<MEMRD
loop
ANDN OUTA, addrRdWrMask ' $FFFF03 e.g.
OR OUTA, addr
ADD addr, #256
OR OUTA, #|<DMAWR ' give 100 ns to read memory
DJNZ rep, #loop ' give 100 ns to send it
It's a useful trick; I had a 32KB SRAM scheme using 2-bits to generate a video stream before the Propeller made that redundant.
If one wants to minimise I/O usage, RAM addressing can be done through an external counter, read via an 8-to-1 multiplexor and output via a 1-to-8 bit settable latch. That slows down access to RAM but the raw DMA can run just as quickly. With a bit of logic on the clocking line ( another counter and some gates ), it should be possible to blat the data across at very high speed by using the internal CTRA/CTRB. Even closer to DMA with the Propeller just providing the clock rate.
Comments
▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
JMH
Will be 250 ns = 4 MByte/s
▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
The more I know, the more I know I don't know.· Is this what they call Wisdom?
If one wants to minimise I/O usage, RAM addressing can be done through an external counter, read via an 8-to-1 multiplexor and output via a 1-to-8 bit settable latch. That slows down access to RAM but the raw DMA can run just as quickly. With a bit of logic on the clocking line ( another counter and some gates ), it should be possible to blat the data across at very high speed by using the internal CTRA/CTRB. Even closer to DMA with the Propeller just providing the clock rate.