logic mode in counters: PHSx as index register?
Fred Hawkins
Posts: 997
Is it possible to use the PHSx registers as index registers that increment once on a single software event?
IF·I read the Counters application note correctly, it seems that a pos edge event (any pin·connected to pin A, going from low to high) could be used to increment·PHSa and PHSb by whatever step value is placed into FRQa and FRQb.
My thought is to have two lock-step pointers to arrays, one in words, another in longs.
Ideally, could the counters be set up so they increment on both pos edges and neg edges? (That would allow a single line in the code to increment two registers).·
Post Edited (Fred Hawkins) : 10/29/2007 12:44:22 PM GMT
IF·I read the Counters application note correctly, it seems that a pos edge event (any pin·connected to pin A, going from low to high) could be used to increment·PHSa and PHSb by whatever step value is placed into FRQa and FRQb.
My thought is to have two lock-step pointers to arrays, one in words, another in longs.
Ideally, could the counters be set up so they increment on both pos edges and neg edges? (That would allow a single line in the code to increment two registers).·
Post Edited (Fred Hawkins) : 10/29/2007 12:44:22 PM GMT
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In assembly, you'd need two instructions to toggle the bit.
my two cents,
Marty
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Lunch cures all problems! have you had lunch?
If you want to do the same thing that Rokicki does, you have to synchronize the cog counters and the cog's instruction stream. It's certainly doable and you can get higher transfer rates, but it's messier, particularly if you have to transfer the data directly to Hub memory.