3.3V/5V bidirectional I/O pin interface
Peter Verkaik
Posts: 3,956
I am about to design a new board that utilizes the 24pin DIL format stamps (5V I/O)
but would like it to be SPIN Stamp (3.3V I/O) compatible as well.
I found a design for the I/O pins as in the attachement.
For the level shift operation three states has to be considered:
· State 1. No device is pulling down the bus line and the bus line of the “Lower voltage” section is pulled up
by its pull-up resistor R1 to 3.3 V. The gate and the source of the MOS-FET are both at 3.3 V, so its VGS
is below the threshold voltage and the MOS-FET is not conducting. This allows that the bus line at the
“Higher voltage” section is pulled up by its pull-up resistor R2 to 5V. So the bus lines of both sections are
HIGH, but at a different voltage level.
· State 2. A 3.3 V device pulls down the bus line to a LOW level. The source of the MOS-FET becomes
also LOW, while the gate stays at 3.3 V. The VGS rises above the threshold and the MOS-FET becomes
conducting. Now the bus line of the “Higher voltage” section is also pulled down to a LOW level by the 3.3
V device via the conducting MOS-FET. So the bus lines of both sections become LOW at the same
voltage level.
· State 3. A 5 V device pulls down the bus line to a LOW level. Via the drain-substrate diode of the MOSFET
the “Lower voltage” section is in first instance pulled down until VGS passes the threshold and the
MOS-FET becomes conducting. Now the bus line of the “Lower voltage” section is further pulled down to
a LOW level by the 5 V device via the conducting MOS-FET. So the bus lines of both sections become
LOW at the same voltage level.
The three states show that the logic levels are transferred in both directions of the bus system, independent of
the driving section. State 2 and state 3 perform the “wired AND” function between the bus lines of both sections
as required by the I2C-bus specification.
I realize there is no 'drive high' option to supply a high output source voltage (eg. to drive led with cathode to GND)
but that is not a problem as it is possible to sink enough current (eg. led connected with anode to VDD2).
Questions:
Is this a safe design to protect Spin Stamp I/O pins (even when VDD1=5V)·?
Is it possible to combine R3 and R4 into a single resistor and on what
side is this single resistor best located (I think at the drain)?
Any timing or·capacitive load limits? BSN10 parameters:
TYPE··· VGS(th)······························· RDS(on)·············· Ciss······ Package
BSN10· min. 0.4V max. 1.8V··· 25 Ohm (typ)·· 15 pF·· TO-92
regards peter
but would like it to be SPIN Stamp (3.3V I/O) compatible as well.
I found a design for the I/O pins as in the attachement.
For the level shift operation three states has to be considered:
· State 1. No device is pulling down the bus line and the bus line of the “Lower voltage” section is pulled up
by its pull-up resistor R1 to 3.3 V. The gate and the source of the MOS-FET are both at 3.3 V, so its VGS
is below the threshold voltage and the MOS-FET is not conducting. This allows that the bus line at the
“Higher voltage” section is pulled up by its pull-up resistor R2 to 5V. So the bus lines of both sections are
HIGH, but at a different voltage level.
· State 2. A 3.3 V device pulls down the bus line to a LOW level. The source of the MOS-FET becomes
also LOW, while the gate stays at 3.3 V. The VGS rises above the threshold and the MOS-FET becomes
conducting. Now the bus line of the “Higher voltage” section is also pulled down to a LOW level by the 3.3
V device via the conducting MOS-FET. So the bus lines of both sections become LOW at the same
voltage level.
· State 3. A 5 V device pulls down the bus line to a LOW level. Via the drain-substrate diode of the MOSFET
the “Lower voltage” section is in first instance pulled down until VGS passes the threshold and the
MOS-FET becomes conducting. Now the bus line of the “Lower voltage” section is further pulled down to
a LOW level by the 5 V device via the conducting MOS-FET. So the bus lines of both sections become
LOW at the same voltage level.
The three states show that the logic levels are transferred in both directions of the bus system, independent of
the driving section. State 2 and state 3 perform the “wired AND” function between the bus lines of both sections
as required by the I2C-bus specification.
I realize there is no 'drive high' option to supply a high output source voltage (eg. to drive led with cathode to GND)
but that is not a problem as it is possible to sink enough current (eg. led connected with anode to VDD2).
Questions:
Is this a safe design to protect Spin Stamp I/O pins (even when VDD1=5V)·?
Is it possible to combine R3 and R4 into a single resistor and on what
side is this single resistor best located (I think at the drain)?
Any timing or·capacitive load limits? BSN10 parameters:
TYPE··· VGS(th)······························· RDS(on)·············· Ciss······ Package
BSN10· min. 0.4V max. 1.8V··· 25 Ohm (typ)·· 15 pF·· TO-92
regards peter
Comments
That's essentially the same circuit as the one from the Philips documentation (posted in the interface sticky).
http://forums.parallax.com/attachment.php?attachmentid=41645
Except the additional 100 ohm resistor you have on the drain side does seem like a good idea, in case by mistake or intent one side ends up driven high while the other is low. That would normally be disallowed in your scheme, I think, but better safe than sorry. If the 3.3 volt side is driven high while the 5 volt side is driven low, a large current would flow through the substrate diode of the mosfet. Similarly a large current would flow through the mosfet if the 5 volt side is driven high while the 3.3 volt side is driven low. The single resistor on the drain side should suffice to limit the current in either case.
The circuit does limit the possibilities of the i/o, not just for LEDs. There are things like sigma-delta that really do require symmetrical drive and/or high speed. The speed penalty will not be significant at I2C speeds, but there will be a cutoff frequency dependent on the RC time of the pullup resistors with the node capacitance. The mosfet is configured in a common gate circuit (gate attached to low impedance Vdd), so it should get pretty close to its stated turnon/off spec in the 10 nS range. But when the driver side changes from low output back to input, the node capacitances have to charge through the pullup resistors, and that will take on the order of microseconds with 4.7kohm * 10pf. That could be speeded up by briefly pulsing the pin high before making it an input. Then the full 100 ma current from the BSN10 could hasten the recharge (Leave in the 100 ohm drain resistor for protection!).
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Tracy Allen
www.emesystems.com