2-pin Sigma-Delta ADC input protection for large voltages...

Rayman

I've just started thinking about using two pins of the Prop to do Sigma-Delta ADC (as in the Microphone2VGA demo).· I'm thinking that this approach could also work for large voltages.· Right now, I'm thinking about up to 200 VDC.

But, this could be a problem when the input signal is present, but the Prop is unpowered or not running the ADC code.

I think the input pins are protected, so this wouldn't be an issue.· Still, I don't really want to count on that.· Plus, I think this raises Vdd or lowers Vss, something I'd rather not do...

So, I'm thinking of putting back-to-back 3.0 V zener diodes in parallel with the two capacitors.·· I think this should be OK since, when the ADC is running, the voltage between capacitors should stay very close to Vdd/2=· 1.65 V.· The self-capacitance of the zeners would be balanced and just add to the real capacitors.

Anybody know a better way?· (Or, think this is a bad approach?)

Beau Schwabe

Even though the I/O protection diodes are pretty robust, I can understand your concern. If anything I would put a current limiting resistor on the input of the sigma delta ADC that would limit the current to a maximum of 50mA based on a 200V input. (<- not where the microphone would be, but near the I/O pin itself.) I think that the back to back Zener diodes would be fine, they would take the ESD protection diodes out of the loop for that I/O pin.

Attached is more or less for reference, but on the left you can see a schematic of basically how the Protection diodes are configured. The NMOS and PMOS transistors form a Diode with a forward voltage drop of about 0.4V ... The reverse Zener effect of the NMOS and PMOS transistors is about 7 Volts.

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Beau Schwabe

IC Layout Engineer
Parallax, Inc.

Post Edited (Beau Schwabe (Parallax)) : 10/16/2007 3:11:11 PM GMT

Rayman

I guess the thing I'd worry about is what happens if +HV input is applied when the Prop and regulator power are off... I guess the bottom left NMOS would clamp to the 7 Volt zener voltage right?

But, does 7 V destroy the Prop? Is this over what the Vdd caps on proto/demo boards rated for?

Beau Schwabe

Rayman,
·
I·included the Zener rating of the NMOS/PMOS transistors, only because they exhibit Zener characteristics.· The internal Zener only effects an·ESD event on the GND terminal when Power and GND are left floating in an attempt to keep the Power and Ground rails relatively close (within 7V) of each other.· An ESD event on the Power terminal when Power and GND are left floating·allows the forward Diode conduction to bring the Power and Ground rails to within 0.4V of each other.· For obvious reasons you cannot have a forward biased diode across the Power and Ground terminals, so in this situation you must rely on the Zener characteristics or other "smart" methods to track and clamp the Power and Ground during an ESD event.


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Beau Schwabe

IC Layout Engineer
Parallax, Inc.

Post Edited (Beau Schwabe (Parallax)) : 10/16/2007 4:12:50 PM GMT

Rayman

I'm thinking now that all I need is one 3 V zener to keep the voltage between ADC capacitors and ground <Vdd at all times. I guess the internal NMOS will clamp negative voltages good enough.

Rayman

Still, I'd want to add the other zener to Vdd to balance the capacitances... Then, I'm back where I started! I think this protects both pins used for ADC. Also, I anticipate the resistor from the HV input to the capacitors to be in the 100K to 1Meg range, keeping max. current well below the 50mA rating...

Tracy Allen

Also take a look at this thread:
http://forums.parallax.com/showthread.php?p=633577

I think the zener to Vss is a good solution. The zener capacitance will probably be much much smaller than the integration capacitors, so balance might not be an issue. Low voltage zeners have a pretty soft knee, so even with a 3.3 volt zener account should be taken of leakage current at 1.65 volts, relative to the signal input current.

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Tracy Allen
www.emesystems.com

Post Edited (Tracy Allen) : 10/16/2007 4:58:57 PM GMT

Rayman

I hadn't thought about the leakage currents... Datasheet says Vdd can go up to 4 V, maybe I'll use a 4V zener instead... Have to research the leakage... I think this leakage would have the affect of shifting the input range from +/- some value towards the + side...