VGA issue

Lee Marshall

I just soldered a VGA socket into my homemade demoboard, and it WORKS!!!!!!!
BUT, it sort of doesnt.
I have been running the demo programs that come with the prop tool, and have found VGA_512x384_Bitmap_Demo.spin to work fine, but VGA_Demo and VGA_Text_Demo dont.
with VGA_Demo:
I get a black screen, and the monitor's light goes from orange to green, as if turning on, then off again.
with VGA_Text_Demo:
I get MODE NOT SUPPORTED.

i altered the clock settings in all the files to use 4MHz with XInput(they were all set to 5MHz).
could it be that the demos just wont work with a 4MHz oscillator?

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I hear and I forget. I see and I remember. I do and I understand
-Confucius

Rayman

Some of the demo's seem to sync at non-standard modes, like 720x400. Try the 1024x768 demo. This is the best mode anyway (if your monitor can handle it).

You can find this by searching this forum (good luck) or here:

http://www.rayslogic.com/propeller/Users/VGA_Tile_Driver_Demo_-_Archive__[noparse][[/noparse]Date_2006.11.12__Time_03.56].zip

Mike Green

I suspect your clock is just too slow for the refresh and video rates needed by the other programs. Is there some reason why you can't use a faster clock using the PLL? A 4MHz input x PLL16 = 64MHz which should work much better.

Lee Marshall

i am using PLL16X, i should have said.

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I hear and I forget. I see and I remember. I do and I understand
-Confucius

bambino

I seem to recall somewhere 80 Mhz was the minimum for one of those drivers!

Lee Marshall

ah..thatll probably be it then, i was gonna replace the xtal anyway.

i might as well use this thread for the following question:
what exactly do the PHSx registers do?
i know the FRQx registers can copy into them, but what actually goes in them?? a frequency?? a multiple???
how can i get the CTR to provide the video gen with 128mhz(im making a custom vid driver)?

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I hear and I forget. I see and I remember. I do and I understand
-Confucius

Ken Peterson

I tried the VGA Demo object with my monitor and it didn't work "out of the box". I had to tweak some of the parameters before I got a stable image on the monitor. Don't recall offhand what the tweaks were, but I think one of them was changing the pixel rate. I was using the Demo Board so I know the clock was 80MHz.

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The more I know, the more I know I don't know.· Is this what they call Wisdom?

bambino

The PHSx increments based on the setting of the FRQx, Take a look at the Counters App, it will explain it all!

Lee Marshall

thanks, i see now.
the problem is, i have to generate a 65mhz signal with a 64mhz xtal, do i have the right train of thought:
I would have to:
-Set PLLA div to /2 (giving an X2 clock(128mhz))
-Do some math 128/65 = 1.97
-Do some more math 2³² / 1.97 = 2180186444
-Put 2180186444 (HEX 81F3014C) in FRQA reg
-Start counter, and put it in internal PLL mode.

this would produce an approximation of 65mhz. or would it?
i assume that i could just use a pixel clock of 64mhz and my monitor would still work(i read the values werent critical), but i would still like to know if this is the way i would use the counter for non-powerof2 frequency synthesis.

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I hear and I forget. I see and I remember. I do and I understand
-Confucius

deSilva

Mr Crowley said...
-Set PLLA div to /2 (giving an X2 clock(128mhz)).

You do neither increase the basic clock by the PLL nor does /2 multiply it by 2

Have a look into the basic diagram of how the counters work in the most instructive AN001.

Lee Marshall

when i said setting the pll to /2 gives an x2 clock, i meant the PLL output clock(PLLx[noparse][[/noparse]31])
ive looked at the diagram, and it seems that the phase comparator alters the voltage to the VCO based on the frequency difference between the system clock, and the divider output.
the way i see it, dividing the VCO output frequency by two, would cause the phase comparator to detect the main clock was faster than the divider output and then increase the voltage to the VCO - increasing its output frequency until (output frequency/2) = system clock frequency.

this is all based around my(quite possibly unreliable) understanding of PLLs. in fact, i hadnt met the term before discovering the prop.

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I hear and I forget. I see and I remember. I do and I understand
-Confucius

deSilva

Your description of the working of the PLL is basically correct. What I was referring to was, that the timer PLL is not connected to the system clock but to the timer event you specify, generally the sign bit of PHSx