Unique 256Kbit SPI RAM memory
Different
Posts: 11
Hello all,
I have found fine chip of the 256Kbit (32K x 8) RAM memory with SPI interface from American Microsystems: N256S0830HDA !
Such IC will save many processor's pins and will add 32KB memory for the Propeller!
I wish to unite 16 IC's by 4 pages for 32K x 32bit through SPI bus with 4 data lines (like high speed SD card).
Like XTREME 512K CARD!
What you think about?
This IC's is offered by their distributor - Future Electronics. FRAM memory of the same volume is high-priced...
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Radio DELANET - modern electronics by own hands!
Post Edited (Radio DELANET) : 10/10/2007 9:12:58 AM GMT
I have found fine chip of the 256Kbit (32K x 8) RAM memory with SPI interface from American Microsystems: N256S0830HDA !
Such IC will save many processor's pins and will add 32KB memory for the Propeller!
I wish to unite 16 IC's by 4 pages for 32K x 32bit through SPI bus with 4 data lines (like high speed SD card).
Like XTREME 512K CARD!
What you think about?
This IC's is offered by their distributor - Future Electronics. FRAM memory of the same volume is high-priced...
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Radio DELANET - modern electronics by own hands!
Post Edited (Radio DELANET) : 10/10/2007 9:12:58 AM GMT
Comments
Plus, i2c drivers already exist in the object exchange.
Anyway a 512kbit EEPROM only takes the two standard i2c programming (p28/p29) lines, and gives 64kbytes - hence an additional 32kb. Granted they are not massively fast, but you can have 8 of them per-i2c-bus.
J
Is there anyone else that sells it ?
Bean.
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www.ramtron.com/doc/Products/Nonvolatile/Nonvolatile.asp?ID=5
No delay writes and still non-volatile. Although the down side is that there is a limit to the number of read cycles before it loses its non-volatility.
Last I checked Ramtron's newest chips claim to be rated for trillions of reads, so this is probably enough.
Just wish more companies pursued this technology too.
Add the battery to RAM is cheaper.
This chips will be sale at retail since November... but in Russia
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Radio DELANET - modern electronics by own hands!
I am not quite sure I understand you:
(a) 16 chips? That's 256k x 32bit
(b) One bus? That means 4 select lines decoded to 1-of-16
or
(b') Four busses? Needing four cogs then... And it will become mre tricky with the select lines..
(c) Lets say one bus and one COG... 20 MHz clock.. you need to send the address = 15 bits and receive 1 byte = 8 bits plus some overhead = 700 kByte/s. Access to HUB is 1 item/200 ns = 5 M items/s
You could do that. That would mean 4 select lines with 4 chips on each select line. You'd need a single clock line for all and 4 data lines (one for each chip on a select line). That's 9 I/O pins. You could reduce that to 8 if you used a 2 to 4 decoder with an enable line. You'd store adjacent nibbles in successive locations in the 4 SRAMs which would be relatively easy if you used paged mode. This could be done easily in a small part of one cog's memory. For that matter, you could use Spin for testing and for applications that don't need very high speed. You could probably get 100Kbps block transfers completely in Spin.
Mike
There is enough only six wires.
Potentially speed must be approximately 2.5MB/s for word write/read mode and up to 10MB/s in page or burst mode for this RAM module.
I hope a Propeller (1 or 2 COGs may be) will manage the task.
I attached some functional diagram for latch address page and first page (128KB) of all memory (512KB).
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Radio DELANET - modern electronics by own hands!
Post Edited (Radio DELANET) : 10/10/2007 11:21:40 AM GMT
Can you explain what the 373 latch is for? Is it needed if you are just using 4 chips?
Thanks,
Doug
This would save you having to decode the address in the assembly routine. The decoder would always be enabled and you'd
use the 3rd line to select the unused outputs so the ones attached to chips would all be disabled.
For speed, I estimate it will take 2us to send a command, 4us to send a 16 bit address, and roughly 3-3.5us to transfer each 32 bit word. For a single 32 bit word, we're talking about roughly 10us. With burst mode, the 6+us overhead is amortized across a longer transfer and the overall speed will approach 3-3.5us per word.
-Phil
373 latch is for retention address of page memory.
I have drawn only ICs N256S0830HDA for one page of memory.
4 pages = 4 x 4 ICs N256S0830HDA
Each page add in by the agency of signals CSx/ (where 'x' is 0, 1, 2, or 3).
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Radio DELANET - modern electronics by own hands!
Yes of course!
My diagram is only common logic structure...
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Radio DELANET - modern electronics by own hands!
-Phil
Post Edited (Phil Pilgrim (PhiPi)) : 10/11/2007 5:35:47 AM GMT
Probably it indeed but small number of wires and low-power is more important for me. It will be RAM module in my portable electronic device similar Palm.
I know 74HC/HCT237 but it hase very high quiescent current...
P.S. Very thanks for advice. I only start to try Propeller but already trust its greater opportunities
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Radio DELANET - modern electronics by own hands!