Using PAR for accessing more than one variable

Harley

So far only one variable has needed to be accessed by ASM from Spin..

I'm using PASD (really works great), I can see the variables I'm using, but the program doesn't 'see' them.

If I write

      mov   ptr,PAR                  ' I can see valid ptr value
      ....
      rdlong temp,ptr                ' gets the value 
      ....
      rdlong temp2,(ptr + 4)     ' doesn't get the next value at ptr + 4; WHY?
' and so on

Is there a better way to do this? If so, what is it called? I couldn't find anything wrong with what I'd planned to use in Prop manual, deSilva's writings, or even using the 'Google search' Seems some details have been skipped for beginning into this area.

Thanks to any and all who can explain this.

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Harley Shanko

Bill Henning

Try:

mov ptr,PAR
...
rdlong temp,ptr
...
add ptr,#4
...
rdlong temp2,ptr


Basically you can't do "(ptr+4)" as ptr holds the address of a pointer, that needs to be incremented by a separate instruction.

Hope this helps,

Bill

Harley said...
So far only one variable has needed to be accessed by ASM from Spin..

I'm using PASD (really works great), I can see the variables I'm using, but the program doesn't 'see' them.

If I write

      mov   ptr,PAR                  ' I can see valid ptr value
      ....
      rdlong temp,ptr                ' gets the value 
      ....
      rdlong temp2,(ptr + 4)     ' doesn't get the next value at ptr + 4; WHY?
' and so on

Is there a better way to do this? If so, what is it called? I couldn't find anything wrong with what I'd planned to use in Prop manual, deSilva's writings, or even using the 'Google search' Seems some details have been skipped for beginning into this area.

Thanks to any and all who can explain this.

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www.mikronauts.com - a new blog about microcontrollers

deSilva

ptr +4 is the register 4 cells behind prt - You have to ADD 4 to ptr to do want you want...

Harley

Shucks,

Anything to slow down ASM. Wish Chip had allowed an offset.

Thanks guys.

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Harley Shanko

deSilva

Oh no! This is a true RISC machine

Post Edited (deSilva) : 10/7/2007 9:48:04 PM GMT

Fred Hawkins

Ah yes, ve like leather, vhips, and violins. Hairshirt, anyone?

potatohead

For sake of discussion, where would the offset go?

Look at the instruction long bits. They are all essentially performing some purpose. More bits then are needed to fetch the offset, and isn't that just the same as fetching another instruction?

Immediate operands, bigger than $1ff are the same way. No instruction bits, so it gets fetched from one of the other COG longs.

Something would have to give, in order for these cases to be written as one instruction. (maybe somebody could entertain a macro assembler...) If instruction words vary, like the cases above, then COG addressing also must vary, or we end up with a lot more wasted bits being fetched to complete instructions that really are two instructions, in terms of operation performed. Thus overall instruction word length either grows, or we get fewer overall instructions. (A lot fewer, as it would take a lot of bits to really make an impact)

The net result of all of that really is more words fetched to perform the same tasks --a net loss in speed, for all but a few cases.

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