How many cycles does SX need to wake up?
william chan
Posts: 1,326
Here's a tricky question for SX experts.
Let's say the SX is asleep, and waiting for serial data to come in on pin rb.0 at 2400 baud.
If the Start Bit were to wake up the SX which runs at 4Mhz, can it wake up fast enough to receive the 1st byte?
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Let's say the SX is asleep, and waiting for serial data to come in on pin rb.0 at 2400 baud.
If the Start Bit were to wake up the SX which runs at 4Mhz, can it wake up fast enough to receive the 1st byte?
▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
www.fd.com.my
www.mercedes.com.my
Comments
I think you'll have some trouble.
The problem is that to wake an SX28 up from sleep with a change on rb.x, it first does a full reset, making all direction pins on all ports inputs which releases any outputs you might have active, and then it triggers the DRT timer which is about 16 milliseconds, to let the oscillator stabilize. After that, it starts executing code at the Reset vector.
The situation for the SX48 is a little different. On exit from sleep, either through a rb.x pin change or MasterClear, the port directions all revert to inputs as on the SX28, but then you have a choice of several DRT timers, from about 300 uSec, 16 mSec, 60 mSec and 960 mSec as I recall. Choosing the 300 uSec would seem the best choice.
The trouble is, the DRT times are VERY VERY temperature and voltage sensitive; I have experienced ranges well in excess of 10 to 1. So the predictability of when the first sample will be taken after wake-from-sleep is almost impossible, and certainly not reliable or very repeatable. This is a serious shortcoming in the chip design.
Personally, I use some of these tricks for data communications, but I wake the SX up prior to data coming along... so in anticipation of data, and then I sample at 3 times the bit rate to snag the first third of the start bit. Then, once that is detected, I set the timings so I sample in the middle third of every succeeding bit. Realize that the sample in the middle of the first data bit after the Start bit is 1 and 1/3 bit times away from detection of the Start bit. Obviously, the middle third of each following bit is one bit time away from the middle of the previous bit.
Hope this helps .
Cheers,
Peter (pjv)
Say Bean, thanks for that link to App note18 regarding Resets. It seems no matter how many times one reads things, there always appears to be something new to learn.
That app note references some values of DRT timings I was not familiar with; I had only tested those available through the "DEVICE" window in the IDE, and there appear to be some other ones. So there may be some pleasant surprises for me, as I too have a need for ultra low power (using sleep) and then a quick, or at least consistent, predictable start up time after triggering a wake-from-sleep on portB.
Thanks for the heads-up!
Cheers,
Peter (pjv)